a000298_approval, dave_user
551
edits
Changes
Pinout WIP
* NAND.<x>: pin connected to the flash NAND
* MTR: pin connected to voltage monitors
* TPM: pin connected to TPM unit <code>SE050</code>
|-
|'''Ball/pin #'''
|J1.15
|CPU_ONOFF
|TBDCPU.ONOFF|TBDG22|TBDNVCC_SNVS_1V8|TBDI/O|TBDinternal pull-up 100k to NVCC_SNVS_1V8
|
|
|J1.17
|CPU_PORn
|TBDCPU.POR_BPMIC.POR_B|TBDJ299|TBDNVCC_SNVS_1V8|TBDI/O|TBDinternal pull-up 100k to NVCC_SNVS_1V8
|
|
|PMIC_ON_REQ
//VMON_RST
|TBDCPU.PMIC_ON_REQPMIC.PMIC_ON_REQ|TBDF2239|TBDNVCC_SNVS_1V8|TBDI/O|TBDoptionally connected tovoltage monitor reset
|
|
|J1.21
|PMIC_RST_B
|TBDPMIC.PMIC_RST_B|TBD8|TBDNVCC_SNVS_1V8|TBDI/O|TBDinternal pull-up 100k to NVCC_SNVS_1V8
|
|
|J1.23
|BOARD_PGOOD
|TBDMTR.RESET_B|TBD2|TBDNVCC_3V3|TBDO|TBD
|
|
|J1.25
|BOOT_MODE0
|CPU.BOOT_MODE0
|G10
|NVCC_3V3
|TBD
|TBDinternal 10k pull-up or pull-down|TBD|TBD|TBDaccording to specific model
|
|
|J1.27
|BOOT_MODE1
|CPU.BOOT_MODE1
|F8
|NVCC_3V3
|TBD
|TBDinternal 10k pull-up or pull-down|TBD|TBD|TBDaccording to specific model
|
|
|J1.29
|BOOT_MODE2
|CPU.BOOT_MODE2
|G8
|NVCC_3V3
|TBD
|TBDinternal 10k pull-up or pull-down|TBD|TBD|TBDaccording to specific model
|
|
|J1.33
|LVDS0_D3_N
|TBDCPU.LVDS0_D3_N|TBDJ28|TBD-|TBDD|TBD
|
|
|J1.35
|LVDS0_D3_P
|TBDCPU.LVDS0_D3_P|TBDH29|TBD-|TBDD|TBD
|
|
|J1.37
|LVDS0_D2_N
|TBDCPU.LVDS0_D2_N|TBDH28|TBD-|TBDD|TBD
|
|
|J1.39
|LVDS0_D2_P
|TBDCPU.LVDS0_D2_P|TBDG29|TBD-|TBDD|TBD
|
|
|J1.41
|LVDS0_CLK_N
|TBDCPU.LVDS0_CLK_N|TBDG28|TBD-|TBDD|TBD
|
|
|J1.43
|LVDS0_CLK_P
|TBDCPU.LVDS0_CLK_P|TBDF29|TBD-|TBDD|TBD|
|
|-
|J1.45
|LVDS0_D1_N
|TBDCPU.LVDS0_D1_N|TBDF28|TBD-|TBDD|TBD
|
|
|J1.47
|LVDS0_D1_P
|TBDCPU.LVDS0_D1_P|TBDE29|TBD-|TBDD|TBD
|
|
|J1.49
|LVDS0_D0_N
|TBDCPU.LVDS0_D0_N|TBDE28|TBD-|TBDD|TBD
|
|
|J1.51
|LVDS0_D0_P
|TBDCPU.LVDS0_D0_P|TBDD29|TBD-|TBDD|TBD
|
|
|J1.55
|LVDS1_D3_N
|TBDCPU.LVDS1_D3_N|TBDD28|TBD-|TBDD|TBD
|
|
|J1.57
|LVDS1_D3_P
|TBDCPU.LVDS1_D3_P|TBDC29|TBD-|TBDD|TBD
|
|
|J1.59
|LVDS1_D2_N
|TBDCPU.LVDS1_D2_N|TBDC28|TBD-|TBDD|TBD
|
|
|J1.61
|LVDS1_D2_P
|TBDCPU.LVDS1_D2_P|TBDB29|TBD-|TBDD|TBD
|
|
|J1.63
|LVDS1_CLK_N
|TBDCPU.LVDS1_CLK_N|TBDB28|TBD-|TBDD|TBD
|
|
|J1.65
|LVDS1_CLK_P
|TBDCPU.LVDS1_CLK_P|TBDA28|TBD-|TBDD|TBD
|
|
|J1.67
|LVDS1_D1_N
|TBDCPU.LVDS1_D1_N|TBDB27|TBD-|TBDD|TBD
|
|
|J1.69
|LVDS1_D1_P
|TBDCPU.LVDS1_D1_P|TBDA27|TBD-|TBDD|TBD
|
|
|J1.71
|LVDS1_D0_N
|TBDCPU.LVDS1_D0_N|TBDB26|TBD-|TBDD|TBD
|
|
|J1.73
|LVDS1_D0_P
|TBDCPU.LVDS1_D0_P|TBDA26|TBD-|TBDD|TBD
|
|
|J1.77
|MIPI_CSI2_D0_P
|TBDCPU.MIPI_CSI2_D0_P|TBDA25|TBD-|TBDD|TBD
|
|
|J1.79
|MIPI_CSI2_D0_N
|TBDCPU.MIPI_CSI2_D0_N|TBDB25|TBD-|TBDD|TBD
|
|
|J1.81
|MIPI_CSI2_D1_P
|TBDCPU.MIPI_CSI2_D1_P|TBDA24|TBD-|TBDD|TBD
|
|
|J1.83
|MIPI_CSI2_D1_N
|TBDCPU.MIPI_CSI2_D1_N|TBDB24|TBD-|TBDD|TBD
|
|
|J1.85
|MIPI_CSI2_CLK_P
|TBDCPU.MIPI_CSI2_CLK_P|TBDA23|TBD-|TBDD|TBD
|
|
|J1.87
|MIPI_CSI2_CLK_N
|TBDCPU.MIPI_CSI2_CLK_N|TBDB23|TBD-|TBDD|TBD
|
|
|J1.89
|MIPI_CSI2_D2_P
|TBDCPU.MIPI_CSI2_D2_P|TBDA22|TBD-|TBDD|TBD
|
|
|J1.91
|MIPI_CSI2_D2_N
|TBDCPU.MIPI_CSI2_D2_N|TBDB22|TBD-|TBDD|TBD|
|
|-
|J1.93
|MIPI_CSI2_D3_P
|TBDCPU.MIPI_CSI2_D3_P|TBDA21|TBD-|TBDD|TBD
|
|
|J1.95
|MIPI_CSI2_D3_N
|TBDCPU.MIPI_CSI2_D3_N|TBDB21|TBD-|TBDD|TBD
|
|
|J1.99
|MIPI_CSI1_D3_P
|TBDCPU.MIPI_CSI1_D3_P|TBDD26|TBD-|TBDD|TBD
|
|
|J1.101
|MIPI_CSI1_D3_N
|TBDCPU.MIPI_CSI1_D3_N|TBDE26|TBD-|TBDD|TBD
|
|
|J1.103
|MIPI_CSI1_D2_P
|TBDCPU.MIPI_CSI1_D2_P|TBDD24|TBD-|TBDD|TBD
|
|
|J1.105
|MIPI_CSI1_D2_N
|TBDCPU.MIPI_CSI1_D2_N|TBDE24|TBD-|TBDD|TBD
|
|
|J1.107
|MIPI_CSI1_CLK_P
|TBDCPU.MIPI_CSI1_CLK_P|TBDD22|TBD-|TBDD|TBD
|
|
|J1.109
|MIPI_CSI1_CLK_N
|TBDCPU.MIPI_CSI1_CLK_N|TBDE22|TBD-|TBDD|TBD
|
|
|J1.111
|MIPI_CSI1_D1_P
|TBDCPU.MIPI_CSI1_D1_P|TBDD20|TBD-|TBDD|TBD
|
|
|J1.113
|MIPI_CSI1_D1_N
|TBDCPU.MIPI_CSI1_D1_N|TBDE20|TBD-|TBDD|TBD
|
|
|J1.115
|MIPI_CSI1_D0_P
|TBDCPU.MIPI_CSI1_D0_P|TBDD18|TBD-|TBDD|TBD
|
|
|J1.117
|MIPI_CSI1_D0_N
|TBDCPU.MIPI_CSI1_D0_N|TBDE18|TBD-|TBDD|TBD
|
|
|J1.121
|MIPI_DSI1_D3_P
|TBDCPU.MIPI_DSI1_D3_P|TBDA20|TBD-|TBDD|TBD
|
|
|J1.123
|MIPI_DSI1_D3_N
|TBDCPU.MIPI_DSI1_D3_N|TBDB20|TBD-|TBDD|TBD
|
|
|J1.125
|MIPI_DSI1_D2_P
|TBDCPU.MIPI_DSI1_D2_P|TBDA19|TBD-|TBDD|TBD
|
|
|J1.127
|MIPI_DSI1_D2_N
|TBDCPU.MIPI_DSI1_D2_N|TBDB19|TBD-|TBDD|TBD
|
|
|J1.129
|MIPI_DSI1_CLK_P
|TBDCPU.MIPI_DSI1_CLK_P|TBDA18|TBD-|TBDD|TBD
|
|
|J1.131
|MIPI_DSI1_CLK_N
|TBDCPU.MIPI_DSI1_CLK_N|TBDB18|TBD-|TBDD|TBD
|
|
|J1.133
|MIPI_DSI1_D1_P
|TBDCPU.MIPI_DSI1_D1_P|TBDA17|TBD-|TBDD|TBD
|
|
|J1.135
|MIPI_DSI1_D1_N
|TBDCPU.MIPI_DSI1_D1_N|TBDB17|TBD-|TBDD|TBD
|
|
|J1.137
|MIPI_DSI1_D0_P
|TBDCPU.MIPI_DSI1_D0_P|TBDA16|TBD-|TBDD|TBD
|
|
|J1.139
|MIPI_DSI1_D0_N
|TBDCPU.MIPI_DSI1_D0_N|TBDB16|TBD-|TBDD|TBD|
|
|-
|J1.143
|JTAG_MOD
|TBDCPU.JTAG_MOD|TBDG20|TBDNVCC_3V3|TBDI/O|TBD
|
|
|J1.145
|JTAG_TCK
|TBDCPU.JTAG_TCK|TBDG18|TBDNVCC_3V3|TBDI/O|TBD
|
|
|J1.147
|JTAG_TDI
|TBDCPU.JTAG_TDI|TBDG16|TBDNVCC_3V3|TBDI|TBD
|
|
|J1.149
|JTAG_TMS
|TBDCPU.JTAG_TMS|TBDG14|TBDNVCC_3V3|TBDI/O|TBD
|
|
|J1.151
|JTAG_TDO
|TBDCPU.JTAG_TDO|TBDF14|TBDNVCC_3V3|TBDO|TBD
|
|
|J1.155
|PCIE_REF_PAD_CLK_P
|TBDCPU.PCIE_REF_PAD_CLK_P|TBDD16|TBD-|TBDD|TBD|
|
|-
|J1.157
|PCIE_REF_PAD_CLK_N
|TBDCPU.PCIE_REF_PAD_CLK_N|TBDE16|TBD-|TBDD|TBD
|
|
|J1.159
|PCIE_TXN_P
|TBDCPU.PCIE_TXN_P|TBDA15|TBD-|TBDD|TBD
|
|
|J1.161
|PCIE_TXN_N
|TBDCPU.PCIE_TXN_N|TBDB15|TBD-|TBDD|TBD
|
|
|J1.163
|PCIE_RXN_P
|TBDCPU.PCIE_RXN_P|TBDA14|TBD-|TBDD|TBD
|
|
|J1.165
|PCIE_RXN_N
|TBDCPU.PCIE_RXN_N|TBDB14|TBD-|TBDD|TBD
|
|
|J1.169
|USB2_VBUS
|TBDUSB2_VBUS|TBD-|TBD-|TBDS|TBDSee USB section for details (5-20V tolerance)
|
|
|J1.171
|USB2_ID
|TBDCPU.USB2_ID|TBDE12|TBDNVCC_3V3|TBDI|TBD
|
|
|J1.173
|USB2_D_P
|TBDCPU.USB2_D_P|TBDD14|TBD-|TBDD|TBD
|
|
|J1.175
|USB2_D_N
|TBDCPU.USB2_D_N|TBDE14|TBD-|TBDD|TBD
|
|
|J1.179
|USB2_TX_P
|TBDCPU.USB2_TX_P|TBDA13|TBD-|TBDD|TBD
|
|
|J1.181
|USB2_TX_N
|TBDCPU.USB2_TX_N|TBDB13|TBD-|TBDD|TBD
|
|
|J1.183
|USB2_RX_P
|TBDCPU.USB2_RX_P|TBDA12|TBD-|TBDD|TBD
|
|
|J1.185
|USB2_RX_N
|TBDCPU.USB2_RX_N|TBDB12|TBD-|TBDD|TBD
|
|
|J1.189
|USB1_VBUS
|TBDUSB1_VBUS|TBD-|TBD-|TBDS|TBDSee USB section for details (5-20V tolerance)
|
|
|J1.191
|USB1_ID
|TBDCPOU.USB1_ID|TBDB11|TBDNVCC_3V3|TBDI|TBD
|
|
|J1.193
|USB1_D_P
|TBDCPU.USB1_D_P|TBDD10|TBD-|TBDD|TBD
|
|
|J1.195
|USB1_D_N
|TBDCPU.USB1_D_N|TBDE10|TBD-|TBDD|TBD
|
|
|J1.199
|USB1_TX_P
|TBDCPU.USB1_TX_P|TBDA10|TBD-|TBDD|TBD
|
|
|J1.201
|USB1_TX_N
|TBDCPU.USB1_TX_N|TBDB10|TBD-|TBDD|TBD
|
|
|J1.203
|USB1_RX_P
|TBDCPU.USB1_RX_P|TBDA9|TBD-|TBDD|TBD
|
|
|J1.205
|USB1_RX_N
|TBDCPU.USB1_RX_N|TBDB9|TBD-|TBDD|TBD
|
|
| rowspan="6" |J1.209
| rowspan="6" |GPIO1_IO08
| rowspan="6" |TBDCPU.GPIO1_IO08| rowspan="6" |TBDA8| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD|Pin ALT-0|GPIO1_IO08
|-
|Pin ALT-1
| rowspan="5" |J1.211
| rowspan="5" |GPIO1_IO11
| rowspan="5" |TBDCPU.GPIO1_IO11| rowspan="5" |TBDD8| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD
|Pin ALT-0
|GPIO1_IO11
| rowspan="6" |J1.213
| rowspan="6" |GPIO1_IO09
| rowspan="6" |TBDCPU.GPIO1_IO09| rowspan="6" |TBDB8| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD
|Pin ALT-0
|GPIO1_IO09
| rowspan="4" |J1.215
| rowspan="4" |GPIO1_IO00
| rowspan="4" |TBDCPU.GPIO1_IO00| rowspan="4" |TBDA7| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD
|Pin ALT-0
|GPIO1_IO00
| rowspan="4" |J1.217
| rowspan="4" |GPIO1_IO01
| rowspan="4" |TBDCPU.GPIO1_IO01| rowspan="4" |TBDE8| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD
|Pin ALT-0
|GPIO1_IO01
| rowspan="3" |J1.219
| rowspan="3" |GPIO1_IO10
| rowspan="3" |TBDCPU.GPIO1_IO10| rowspan="3" |TBDB7| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD
|Pin ALT-0
|GPIO1_IO10
| rowspan="3" |J1.221
| rowspan="3" |GPIO1_IO13
| rowspan="3" |TBDCPU.GPIO1_IO13| rowspan="3" |TBDA6| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD
|Pin ALT-0
|GPIO1_IO13
| rowspan="3" |J1.223
| rowspan="3" |GPIO1_IO12
| rowspan="3" |TBDCPU.GPIO1_IO12| rowspan="3" |TBDA5| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD|Pin ALT-0|GPIO1_IO12
|-
|Pin ALT-1
| rowspan="5" |J1.225
| rowspan="5" |GPIO1_IO07
| rowspan="5" |TBDCPU.GPIO1_IO07| rowspan="5" |TBDF6| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD
|Pin ALT-0
|GPIO1_IO07
| rowspan="5" |J1.227
| rowspan="5" |GPIO1_IO15
| rowspan="5" |TBDCPU.GPIO1_IO15| rowspan="5" |TBDB5| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD
|Pin ALT-0
|GPIO1_IO15
| rowspan="5" |J1.229
| rowspan="5" |GPIO1_IO14
| rowspan="5" |TBDCPU.GPIO1_IO14| rowspan="5" |TBDA4| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD
|Pin ALT-0
|GPIO1_IO14
| rowspan="4" |J1.231
| rowspan="4" |GPIO1_IO05
| rowspan="4" |TBDCPU.GPIO1_IO05| rowspan="4" |TBDB4| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD
|Pin ALT-0
|GPIO1_IO05
| rowspan="5" |J1.233
| rowspan="5" |GPIO1_IO06
| rowspan="5" |TBDCPU.GPIO1_IO06| rowspan="5" |TBDA3| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD
|Pin ALT-0
|GPIO1_IO06
|J1.237
|ETH0_TXRX3_M
|TBDLAN.TXTRM_D|TBD11|TBD-|TBDD|TBD
|
|
|J1.239
|ETH0_TXRX3_P
|TBDLAN.TXTRP_D|TBD10|TBD-|TBDD|TBD
|
|
|J1.241
|ETH0_TXRX2_M
|TBDLAN.TXTRM_C|TBD8|TBD-|TBDD|TBD
|
|
|J1.243
|ETH0_TXRX2_P
|TBDLAN.TXTRP_C|TBD7|TBD-|TBDD|TBD
|
|
|J1.245
|ETH0_TXRX1_M
|TBDLAN.TXTRM_B|TBD6|TBD-|TBDD|TBD
|
|
|J1.247
|ETH0_TXRX1_P
|TBDLAN.TXTRP_B|TBD5|TBD-|TBDD|TBD
|
|
|J1.249
|ETH0_TXRX0_M
|TBDLAN.TXTRM_A|TBD3|TBD-|TBDD|TBD|
|
|-
|J1.251
|ETH0_TXRX0_P
|TBDLAN.TXTRP_A|TBD2|TBD-|TBDD|TBD
|
|
|J1.255
|ETH0_LED1
|TBDLAN.LED2|TBD15|TBDVDD_1V8|TBDO|TBDMust be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
|J1.257
|ETH0_LED2
|TBDLAN.LED1/PME_N1|TBD17|TBDVDD_1V8|TBDO|TBDMust be level translated if used @ 3V3Internally pulled-up to 1.8V during bootstrap
|
|
| rowspan="5" |J1.16
| rowspan="5" |SD1_CLK
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_CLK
| rowspan="5" |J1.18
| rowspan="5" |SD1_CMD
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_CMD
| rowspan="5" |J1.20
| rowspan="5" |SD1_DATA0
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA0
| rowspan="5" |J1.22
| rowspan="5" |SD1_DATA1
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA1
| rowspan="5" |J1.24
| rowspan="5" |SD1_DATA2
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD|Pin ALT-0
|USDHC1_DATA2
|-
| rowspan="5" |J1.26
| rowspan="5" |SD1_DATA3
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA3
| rowspan="5" |J1.28
| rowspan="5" |SD1_DATA4
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA4
| rowspan="5" |J1.30
| rowspan="5" |SD1_DATA5
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA5
| rowspan="6" |J1.32
| rowspan="6" |SD1_DATA6
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_SD1| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|USDHC1_DATA6
| rowspan="5" |J1.34
| rowspan="5" |SD1_DATA7
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_DATA7
| rowspan="5" |J1.36
| rowspan="5" |SD1_RESET_B
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD1| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC1_RESET_B
| rowspan="4" |J1.38
| rowspan="4" |SD1_STROBE
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_SD1| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|USDHC1_STROBE
| rowspan="2" |J1.42
| rowspan="2" |SD2_CD_B
| rowspan="2" |CPU.
| rowspan="2" |TBD
| rowspan="2" |TBDNVCC_SD2| rowspan="2" |TBDI/O| rowspan="2" |TBD| rowspan="2" |TBD
|Pin ALT-0
|USDHC2_CD_B
| rowspan="4" |J1.44
| rowspan="4" |SD2_CLK
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_SD2| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD|Pin ALT-0|USDHC2_CLK
|-
|Pin ALT-2
| rowspan="5" |J1.46
| rowspan="5" |SD2_CMD
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD2| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC2_CMD
| rowspan="5" |J1.48
| rowspan="5" |SD2_DATA0
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD2| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC2_DATA0
| rowspan="5" |J1.50
| rowspan="5" |SD2_DATA1
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD2| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC2_DATA1
| rowspan="5" |J1.52
| rowspan="5" |SD2_DATA2
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_SD2| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|USDHC2_DATA2
| rowspan="6" |J1.54
| rowspan="6" |SD2_DATA3
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_SD2| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|USDHC2_DATA3
| rowspan="3" |J1.56
| rowspan="3" |SD2_RESET_B
| rowspan="3" |CPU.
| rowspan="3" |TBD
| rowspan="3" |TBDNVCC_SD2| rowspan="3" |TBDI/O| rowspan="3" |TBD| rowspan="3" |TBD
|Pin ALT-0
|USDHC2_RESET_B
| rowspan="3" |J1.58
| rowspan="3" |SD2_WP
| rowspan="3" |CPU.
| rowspan="3" |TBD
| rowspan="3" |TBDNVCC_SD2| rowspan="3" |TBDI/O| rowspan="3" |TBD| rowspan="3" |TBD
|Pin ALT-0
|USDHC2_WP
|Pin ALT-6
|CORESIGHT_EVENTI
|-
|J1.58
(both NAND and
NOR on board)
|SD2_WP
|CPU.
|TBD
|NVCC_SD2
|O
|internal use for
NAND/NOR selection,
do not connect
|
|
|-
|J1.60
|J1.62
|CLKIN1
|CPU.
|TBD
|TBDNVCC_3V3|TBDI|TBD|TBD
|
|
|J1.64
|CLKIN2
|CPU.
|TBD
|TBDNVCC_3V3|TBDI|TBD|TBD
|
|
|J1.68
|CLKOUT1
|CPU.
|TBD
|TBDNVCC_3V3|TBDO|TBD|TBD
|
|
|J1.70
|CLKOUT2
|CPU.
|TBD
|TBDNVCC_3V3|TBDO|TBD|TBD
|
|
| rowspan="4" |J1.74
| rowspan="4" |HDMI_CEC
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|HDMIMIX_EARC_CEC
| rowspan="4" |J1.76
| rowspan="4" |HDMI_DDC_SCL
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|HDMIMIX_EARC_SCL
| rowspan="4" |J1.78
| rowspan="4" |HDMI_DDC_SDA
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|HDMIMIX_EARC_SDA
| rowspan="5" |J1.80
| rowspan="5" |HDMI_HPD
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|HDMIMIX_EARC_DC_HPD
|J1.84
|HDMI_TXC_N
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.86
|HDMI_TXC_P
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.88
|HDMI_TX0_N
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.90
|HDMI_TX0_P
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.92
|HDMI_TX1_N
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.94
|HDMI_TX1_P
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.96
|HDMI_TX2_N
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.98
|HDMI_TX2_P
|CPU.
|TBD
|TBD-|TBDD|TBD|TBD
|
|
|J1.102
|EARC_P_UTIL
|CPU.
|TBD
|TBDVDDA_1V8|TBDD|TBD|TBD
|
|
|J1.104
|EARC_N_HPD
|CPU.
|TBD
|TBDVDDA_1V8|TBDD|TBD|TBD
|
|
|J1.106
|EARC_AUX
|CPU.
|TBD
|TBDVDDA_1V8|TBDI/O|TBD|TBD
|
|
| rowspan="5" |J1.110
| rowspan="5" |ECSPI1_MISO
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI1_MISO
| rowspan="5" |J1.112
| rowspan="5" |ECSPI1_MOSI
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI1_MOSI
| rowspan="5" |J1.114
| rowspan="5" |ECSPI1_SCLK
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI1_SCLK
| rowspan="5" |J1.116
| rowspan="5" |ECSPI1_SS0
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI1_SS0
| rowspan="6" |J1.120
| rowspan="6" |ECSPI2_MISO
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD|Pin ALT-0
|ECSPI2_MISO
|-
| rowspan="5" |J1.122
| rowspan="5" |ECSPI2_MOSI
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI2_MOSI
| rowspan="5" |J1.124
| rowspan="5" |ECSPI2_SCLK
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI2_SCLK
| rowspan="5" |J1.126
| rowspan="5" |ECSPI2_SS0
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|ECSPI2_SS0
| rowspan="4" |SPDIF_EXT_CLK//
ISP_FL_TRIG_0
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SPDIF_EXT_CLK
| rowspan="6" |SPDIF_RX//
ISP_SHUTTER_TRIG_0
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SPDIF_IN
| rowspan="6" |SPDIF_TX//
ISP_FLASH_TRIG_0
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SPDIF_OUT
| rowspan="7" |J1.138
| rowspan="7" |SAI2_MCLK
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_MCLK
| rowspan="6" |J1.140
| rowspan="6" |SAI2_RXC
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_RX_BCLK
| rowspan="7" |J1.142
| rowspan="7" |SAI2_RXD0
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD|Pin ALT-0|AUDIOMIX_SAI2_RX_DATA[0]
|-
|Pin ALT-1
| rowspan="7" |J1.144
| rowspan="7" |SAI2_RXFS
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_RX_SYNC
| rowspan="5" |J1.146
| rowspan="5" |SAI2_TXC
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_TX_BCLK
| rowspan="6" |J1.148
| rowspan="6" |SAI2_TXD0
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_TX_DATA[0]
| rowspan="7" |J1.150
| rowspan="7" |SAI2_TXFS
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI2_TX_SYNC
| rowspan="6" |SAI3_MCLK//
ISP_PRELIGHT_TRIG_0
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_MCLK
| rowspan="7" |SAI3_RXC//
ISP_SHUTTER_OPEN_0
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_RX_BCLK
| rowspan="6" |SAI3_RXD//
ISP_FL_TRIG_1
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_RX_DATA[0]
| rowspan="7" |SAI3_RXFS//
ISP_SHUTTER_TRIG_1
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_RX_SYNC
| rowspan="7" |SAI3_TXC//
ISP_FLASH_TRIG_1
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD|Pin ALT-0
|AUDIOMIX_SAI3_TX_BCLK
|-
| rowspan="7" |SAI3_TXD//
ISP_PRELIGHT_TRIG_1
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_TX_DATA[0]
| rowspan="7" |SAI3_TXFS//
ISP_SHUTTER_OPEN_1
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI3_TX_SYNC
| rowspan="6" |J1.166
| rowspan="6" |SAI5_MCLK
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_MCLK
| rowspan="6" |J1.168
| rowspan="6" |SAI5_RXC
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_RX_BCLK
| rowspan="6" |SAI5_RXD0//
ISO_14443_LA
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[0]
| rowspan="7" |SAI5_RXD1//
ISO_14443_LB
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[1]
| rowspan="7" |SAI5_RXD2//
ISO_7816_CLK
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[2]
| rowspan="7" |SAI5_RXD3//
ISO_7816_RST_N
| rowspan="7" |CPU.
| rowspan="7" |TBD
| rowspan="7" |TBDNVCC_3V3| rowspan="7" |TBDI/O| rowspan="7" |TBD| rowspan="7" |TBD
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[3]
| rowspan="5" |SAI5_RXFS//
SE050_ENA
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD|Pin ALT-0|AUDIOMIX_SAI5_RX_SYNC
|-
|Pin ALT-1
| rowspan="4" |J1.182
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_MCLK
| rowspan="4" |J1.184
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_BCLK
| rowspan="5" |J1.186
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[0]
| rowspan="4" |J1.188
| rowspan="4" |SAI1_RXD1
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[1]
| rowspan="5" |J1.190
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[2]
| rowspan="5" |J1.192
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[3]
| rowspan="5" |J1.194
| rowspan="5" |SAI1_RXD4
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[4]
| rowspan="6" |J1.196
| rowspan="6" |SAI1_RXD5
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[5]
| rowspan="5" |J1.198
| rowspan="5" |SAI1_RXD6
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[6]
|-
| rowspan="6" |J1.200
| rowspan="6" |SAI1_RXD7
| rowspan="6" |CPU.
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_DATA[7]
| rowspan="3" |J1.202
| rowspan="3" |SAI1_RXFS
| rowspan="3" |CPU.
| rowspan="3" |TBD
| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD| rowspan="3" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_RX_SYNC
| rowspan="4" |J1.204
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_BCLK
| rowspan="4" |J1.206
| rowspan="4" |SAI1_TXD0
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[0]
| rowspan="4" |J1.208
| rowspan="4" |SAI1_TXD1
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[1]
| rowspan="4" |J1.210
| rowspan="4" |SAI1_TXD2
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[2]
| rowspan="4" |J1.212
| rowspan="4" |SAI1_TXD3
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[3]
| rowspan="5" |J1.214
| rowspan="5" |SAI1_TXD4
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[4]
| rowspan="5" |J1.216
| rowspan="5" |SAI1_TXD5
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD|Pin ALT-0|AUDIOMIX_SAI1_TX_DATA[5]
|-
|Pin ALT-1
| rowspan="5" |J1.218
| rowspan="5" |SAI1_TXD6
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[6]
| rowspan="5" |J1.220
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_DATA[7]
| rowspan="4" |J1.222
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|AUDIOMIX_SAI1_TX_SYNC
|
|
|
|-
|J1.226
(TPM on board)
|I2C1_SCL//
I2C_SCL_SE050
|TPM.ISO 7816 IO2
|16
|TPM_VOUT
|I/O
|
|TBD
|
|-
| rowspan="4" |J1.226
| rowspan="4" |I2C1_SCL//I2C_SCL_SE050| rowspan="4" |TBDCPU.I2C1_SCL| rowspan="4" |TBD| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD|Pin ALT-0|I2C1_SCL|-|Pin ALT-1|ENET_QOS_MDC|-|Pin ALT-3|ECSPI1_SCLK|-|Pin ALT-5|GPIO5_IO[14]|-|J1.228(TPM on board)|I2C1_SDA// I2C_SDA_SE050|TPM.ISO 7816 IO1|3|TPM_VOUT|I/O||TBD|
|-
| rowspan="4" |J1.228
| rowspan="4" |I2C1_SDA//
I2C_SDA_SE050
| rowspan="4" |CPU.I2C1_SDA
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|I2C1_SDA
| rowspan="6" |J1.230
| rowspan="6" |I2C2_SCL
| rowspan="6" |CPU.I2C2_SCL
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|I2C2_SCL
| rowspan="5" |J1.232
| rowspan="5" |I2C2_SDA
| rowspan="5" |CPU.I2C2_SDA
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|I2C2_SDA
| rowspan="5" |J1.234
| rowspan="5" |I2C3_SCL
| rowspan="5" |CPU.I2C3_SCL
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|I2C3_SCL
| rowspan="5" |J1.236
| rowspan="5" |I2C3_SDA
| rowspan="5" |CPU.I2C3_SDA
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|I2C3_SDA
| rowspan="5" |J1.238
| rowspan="5" |I2C4_SCL
| rowspan="5" |CPU.I2C4_SCL
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|I2C4_SCL
| rowspan="4" |J1.240
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|I2C4_SDA
| rowspan="3" |J1.244
| rowspan="3" |UART1_RXD
| rowspan="3" |CPU.UART1_RXD
| rowspan="3" |TBD
| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD| rowspan="3" |TBD
|Pin ALT-0
|UART1_RX
| rowspan="3" |J1.246
| rowspan="3" |UART1_TXD
| rowspan="3" |CPU.UART1_TXD
| rowspan="3" |TBD
| rowspan="3" |TBDNVCC_3V3| rowspan="3" |TBDI/O| rowspan="3" |TBD| rowspan="3" |TBD
|Pin ALT-0
|UART1_TX
| rowspan="4" |J1.248
| rowspan="4" |UART2_RXD
| rowspan="4" |CPU.UART2_RXD
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|UART2_RX
| rowspan="4" |J1.250
| rowspan="4" |UART2_TXD
| rowspan="4" |CPU.UART2_TXD
| rowspan="4" |TBD
| rowspan="4" |TBDNVCC_3V3| rowspan="4" |TBDI/O| rowspan="4" |TBD| rowspan="4" |TBD
|Pin ALT-0
|UART2_TX
| rowspan="6" |J1.252
| rowspan="6" |UART3_RXD
| rowspan="6" |CPU.UART3_RXD
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|UART3_RX
| rowspan="6" |J1.254
| rowspan="6" |UART3_TXD
| rowspan="6" |CPU.UART3_TXD
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|UART3_TX
| rowspan="6" |J1.256
| rowspan="6" |UART4_RXD
| rowspan="6" |CPU.UART4_RXD
| rowspan="6" |TBD
| rowspan="6" |TBDNVCC_3V3| rowspan="6" |TBDI/O| rowspan="6" |TBD| rowspan="6" |TBD
|Pin ALT-0
|UART4_RX
| rowspan="5" |J1.258
| rowspan="5" |UART4_TXD
| rowspan="5" |CPU.UART4_TXD
| rowspan="5" |TBD
| rowspan="5" |TBDNVCC_3V3| rowspan="5" |TBDI/O| rowspan="5" |TBD| rowspan="5" |TBD
|Pin ALT-0
|UART4_TX
