a000298_approval, dave_user
299
edits
Changes
→SODIMM J1 EVEN pins declaration
| rowspan="4" |GPIO1_IO02
| rowspan="4" |CPU.GPIO1_IO02
| rowspan="4" |AG13
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Internally used for SW resetPMIC WDI, do not connect
|ALT0
|GPIO1_IO02
|
|-
| rowspan="45" |J1.32| rowspan="45" |SAI3_RXD| rowspan="45" |CPU.SAI3_RXD| rowspan="45" |AF7| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI3_RX_DATA0
|ALT2
|SAI5_RX_DATA0
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)
|-
|ALT4
|UART2_RTS_B
(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
|-
|ALT5
| rowspan="3" |SAI2_MCLK
| rowspan="3" |CPU.SAI2_MCLK
| rowspan="3" |AD19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|ALT1
|SAI5_MCLK
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
|-
|ALT5
|GPIO4_IO27
|-
| rowspan="45" |J1.36| rowspan="45" |SAI3_RXFS| rowspan="45" |CPU.SAI3_RXFS| rowspan="45" |AG8| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI3_RX_SYNC
|ALT2
|SAI5_RX_SYNC
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)
|-
|ALT3
|SAI3_RX_DATA1
|-
|ALT5
