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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

275 bytes removed, 13:30, 22 January 2021
→‎SODIMM J1 EVEN pins declaration
|PMIC_LICELL
|PMIC.LICELL
|3046
| -
|S
|CPU_ONOFF
|CPU.ONOFF
|W21A25|NVCC_SNVSNVCC_SNVS_1V8
|I
|internal pull-up 100k to NVCC_SNVSNVCC_SNVS_1V8
|
|
|CPU_PORn
|CPU.POR_B
PMIC.RESETMCURESET_MCU|W20B24321|NVCC_SNVSNVCC_SNVS_1V8
|I/O
|internal pull-up 100k to NVCC_SNVSNVCC_SNVS_1V8
|
|
|-
|J1.24
|EXT_RESETPMIC_PWRON|MASTER RESETPMIC.PWRON| -22
| -
|I
|internal pull-up 100k to NVCC_SNVSVIN
|
|
|-
| rowspan="45" |J1.26| rowspan="45" |SAI3_RXC| rowspan="45" |CPU.SAI3_RXC| rowspan="45" |F4AG7| rowspan="45" |NVCC_3V3| rowspan="45" |I/O| rowspan="45" |
|ALT0
|SAI3_RX_BCLK
|-
|ALT1
|GPT1_CAPTURE2GPT1_CLK
|-
|ALT2
|SAI5_RX_BCLK
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)
|-
|ALT4
|UART2_CTS_B
|-
|ALT5
| rowspan="4" |GPIO1_IO02
| rowspan="4" |CPU.GPIO1_IO02
| rowspan="4" |R4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |SAI3_RXD
| rowspan="4" |CPU.SAI3_RXD
| rowspan="4" |F3
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="3" |SAI2_MCLK
| rowspan="3" |CPU.SAI2_MCLK
| rowspan="3" |H5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="4" |SAI3_RXFS
| rowspan="4" |CPU.SAI3_RXFS
| rowspan="4" |G4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |I2C3_SCL
| rowspan="4" |CPU.I2C3_SCL
| rowspan="4" |G8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |SAI3_TXFS
| rowspan="4" |CPU.SAI3_TXFS
| rowspan="4" |G3
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="3" |SPDIF_RX
| rowspan="3" |CPU.SPDIF_RX
| rowspan="3" |G6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SPDIF_TX
| rowspan="3" |CPU.SPDIF_TX
| rowspan="3" |F6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="4" |SAI3_MCLK
| rowspan="4" |CPU.SAI3_MCLK
| rowspan="4" |D3
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |I2C3_SDA
| rowspan="4" |CPU.I2C3_SDA
| rowspan="4" |E9
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |SAI3_TXC
| rowspan="4" |CPU.SAI3_TXC
| rowspan="4" |C4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |SAI3_TXD
| rowspan="4" |CPU.SAI3_TXD
| rowspan="4" |C3
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="2" |GPIO1_IO10
| rowspan="2" |CPU.GPIO1_IO10
| rowspan="2" |M7
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="4" |SAI5_MCLK
| rowspan="4" |CPU.SAI5_MCLK
| rowspan="4" |K4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |GPIO1_IO15
| rowspan="4" |CPU.GPIO1_IO15
| rowspan="4" |J6
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="3" |SAI5_RXFS
| rowspan="3" |CPU.SAI5_RXFS
| rowspan="3" |N4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI5_RXC
| rowspan="3" |CPU.SAI5_RXC
| rowspan="3" |L5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI2_TXC
| rowspan="3" |CPU.SAI2_TXC
| rowspan="3" |J5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI2_TXD0
| rowspan="3" |CPU.SAI2_TXD0
| rowspan="3" |G5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI2_TXFS
| rowspan="3" |CPU.SAI2_TXFS
| rowspan="3" |H4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI2_RXD0
| rowspan="3" |CPU.SAI2_RXD0
| rowspan="3" |H6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |SAI5_RXD0
| rowspan="3" |CPU.SAI5_RXD0
| rowspan="3" |M5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="5" |SAI5_RXD1
| rowspan="5" |CPU.SAI5_RXD1
| rowspan="5" |L4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |SAI5_RXD2
| rowspan="5" |CPU.SAI5_RXD2
| rowspan="5" |M4
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |SAI5_RXD3
| rowspan="5" |CPU.SAI5_RXD3
| rowspan="5" |K5
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
|CLK2_N
|CPU.CLK2_N
|T22
|VDDA_1V8
|D
|CLK2_P
|CPU.CLK2_P
|U22
|VDDA_1V8
|D
|PCIE1_REF_CLKN
|CPU.PCIE1_REF_PAD_CLK_N
|K24
|VDD_PHY_3V3
|D
|PCIE1_REF_CLKP
|CPU.PCIE1_REF_PAD_CLK_P
|K25
|VDD_PHY_3V3
|D
|PCIE1_RXN
|CPU.PCIE1_RXN_N
|H24
|VDD_PHY_3V3
|D
|PCIE1_RXP
|CPU.PCIE1_RXN_P
|H25
|VDD_PHY_3V3
|D
|PCIE1_TXN
|CPU.PCIE1_TXN_N
|J24
|VDD_PHY_3V3
|D
|PCIE1_TXP
|CPU.PCIE1_TXN_P
|J25
|VDD_PHY_3V3
|D
|CSI1_CLK_N
|CPU.MIPI_CSI1_CLK_N
|A22
| -
|D
|CSI1_CLK_P
|CPU.MIPI_CSI1_CLK_P
|B22
| -
|D
|CSI1_D0_N
|CPU.MIPI_CSI1_D0_N
|A23
| -
|D
|CSI1_D0_P
|CPU.MIPI_CSI1_D0_P
|B23
| -
|D
|CSI1_D1_N
|CPU.MIPI_CSI1_D1_N
|C22
| -
|D
|CSI1_D1_P
|CPU.MIPI_CSI1_D1_P
|D22
| -
|D
|CSI1_D2_N
|CPU.MIPI_CSI1_D2_N
|B24
| -
|D
|CSI1_D2_P
|CPU.MIPI_CSI1_D2_P
|C23
| -
|D
|CSI1_D3_N
|CPU.MIPI_CSI1_D3_N
|C21
| -
|D
|CSI1_D3_P
|CPU.MIPI_CSI1_D3_P
|D21
| -
|D
|NAND_DQS
|CPU.NAND_DQS
|M20
|NVCC_3V3
|I/O
| rowspan="3" |NAND_DQS
| rowspan="3" |CPU.NAND_DQS
| rowspan="3" |M20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|NAND_ALE
|CPU.NAND_ALE
|G19
|NVCC_3V3
|I/O
| rowspan="3" |NAND_ALE
| rowspan="3" |CPU.NAND_ALE
| rowspan="3" |G19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_CLK
| rowspan="2" |CPU.SD1_CLK
| rowspan="2" |L25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_CE0_B
| rowspan="3" |CPU.NAND_CE0_B
| rowspan="3" |H19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_CMD
| rowspan="2" |CPU.SD1_CMD
| rowspan="2" |L24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_CE1_B
| rowspan="3" |CPU.NAND_CE1_B
| rowspan="3" |G21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_RST_B
| rowspan="2" |CPU.SD1_RST_B
| rowspan="2" |R24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_CE2_B
| rowspan="3" |CPU.NAND_CE2_B
| rowspan="3" |F21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_STROBE
| rowspan="2" |CPU.SD1_STROBE
| rowspan="2" |T24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_CE3_B
| rowspan="3" |CPU.NAND_CE3_B
| rowspan="3" |H20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|NAND_CLE
|CPU.NAND_CLE
|H21
|NVCC_3V3
|I/O
| rowspan="3" |NAND_CLE
| rowspan="3" |CPU.NAND_CLE
| rowspan="3" |H21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA0
| rowspan="2" |CPU.SD1_DATA0
| rowspan="2" |M25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA00
| rowspan="3" |CPU.NAND_DATA00
| rowspan="3" |G20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA1
| rowspan="2" |CPU.SD1_DATA1
| rowspan="2" |M24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA01
| rowspan="3" |CPU.NAND_DATA01
| rowspan="3" |J20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA2
| rowspan="2" |CPU.SD1_DATA2
| rowspan="2" |N25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA02
| rowspan="3" |CPU.NAND_DATA02
| rowspan="3" |H22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA3
| rowspan="2" |CPU.SD1_DATA3
| rowspan="2" |P25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA03
| rowspan="3" |CPU.NAND_DATA03
| rowspan="3" |J21
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA4
| rowspan="2" |CPU.SD1_DATA4
| rowspan="2" |N24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA04
| rowspan="3" |CPU.NAND_DATA04
| rowspan="3" |L20
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA5
| rowspan="2" |CPU.SD1_DATA5
| rowspan="2" |P24
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA05
| rowspan="3" |CPU.NAND_DATA05
| rowspan="3" |J22
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA6
| rowspan="2" |CPU.SD1_DATA6
| rowspan="2" |R25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA06
| rowspan="3" |CPU.NAND_DATA06
| rowspan="3" |L19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="2" |SD1_DATA7
| rowspan="2" |CPU.SD1_DATA7
| rowspan="2" |T25
| rowspan="2" |NVCC_3V3
(NVCC_1V8 on request)
| rowspan="3" |NAND_DATA07
| rowspan="3" |CPU.NAND_DATA07
| rowspan="3" |M19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|NAND_RE_B
|CPU.NAND_RE_B
|K19
|NVCC_3V3
|I/O
| rowspan="3" |NAND_RE_B
| rowspan="3" |CPU.NAND_RE_B
| rowspan="3" |K19
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|NAND_READY_B
|CPU.NAND_READY_B
|K20
|NVCC_3V3
|I/O
| rowspan="2" |NAND_READY_B
| rowspan="2" |CPU.NAND_READY_B
| rowspan="2" |K20
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|NAND_WE_B
|CPU.NAND_WE_B
|K22
|NVCC_3V3
|I/O
| rowspan="2" |NAND_WE_B
| rowspan="2" |CPU.NAND_WE_B
| rowspan="2" |K22
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|NAND_WP_B
|CPU.NAND_WP_B
|K21
|NVCC_3V3
|I/O
| rowspan="2" |NAND_WP_B
| rowspan="2" |CPU.NAND_WP_B
| rowspan="2" |K21
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|-
|J1.166
|CLK1_N
|CPU.CLK1_N
|T23
|
|D|||I/O
|
|
|-
|J1.168
|CLK1_P
|CPU.CLK1_P
|R23
|
|D|||I/O
|
|
|-
|J1.170
|USB2_RXN
|CPU.USB2_RX_N
|B8
|
|D|||I/O
|
|
|-
|J1.172
|USB2_RXP
|CPU.USB2_RX_P
|A8
|
|D|||I/O
|
|
|-
|J1.174
|USB2_TXN
|CPU.USB2_TX_N
|B9
|
|D|||I/O
|
|
|-
|J1.176
|USB2_TXP
|CPU.USB2_TX_P
|A9
|
|D|||I/O
|
|
|-
|J1.178
|USB1_RXN
|CPU.USB1_RX_N
|B12
|
|D
|
|
|
|I/O||||-
|J1.180
|USB1_RXP
|CPU.USB1_RX_P
|A12
|
|D|||I/O
|
|
|-
|J1.182
|USB1_TXN
|CPU.USB1_TX_N
|B13
|
|D|||I/O
|
|
|-
|J1.184
|USB1_TXP
|CPU.USB1_TX_P
|A13
|
|D|||I/O
|
|
|USB1_VBUS
|CPU.USB1_VBUS
|D14F22| -
|S
|Connected with 30K resistor
|
|
|USB2_VBUS
|CPU.USB2_VBUS
|D9F23| -
|S
|Connected with 30K resistor
|
|
|USB1_ID
|CPU.USB1_ID
|C14D22|VDD_PHY_3V3VDDA_1V8
|I
|
|USB2_ID
|CPU.USB2_ID
|C9D23|VDD_PHY_3V3VDDA_1V8
|I
|
|USB1_DN
|CPU.USB1_DN
|B14A22
| -
|D
|USB1_DP
|CPU.USB1_DP
|A14B22
| -
|D
|USB2_DP
|CPU.USB2_DP
|A10B23
| -
|D
|USB2_DN
|CPU.USB2_DN
|B10A23
| -
|D
U0005
a000298_approval, dave_user
299
edits
Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/12665"

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