a000298_approval, dave_user
299
edits
Changes
→SODIMM J1 ODD pins declaration
|GPIO2_IO19
|-
| rowspan="4" |J1.101|HDMI_DDC_SCLrowspan="4" |I2C2_SCL| rowspan="4" |CPU.HDMI_DDC_SCLI2C2_SCL|rowspan="4" |D10|VDD_PHY_1V8rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SCL
|-
|J1.103|HDMI_DDC_SDA|CPU.HDMI_DDC_SDA||VDD_PHY_1V8|I/O||ALT1|ENET1_1588_EVENT1_IN
|-
|ALT2|USDHC3_CD_B(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO5_IO16|-| rowspan="4" |J1.103| rowspan="4" |I2C2_SDA| rowspan="4" |CPU.I2C2_SDA| rowspan="4" |D9| rowspan="4" |NVCC_3V3| rowspan="4" |I/O| rowspan="4" ||ALT0|I2C2_SDA|-|ALT1|ENET1_1588_EVENT1_OUT|-|ALT2|USDHC3_WP(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)|-|ALT5|GPIO5_IO17|-| rowspan="6" |J1.105|HDMI_AUX_Nrowspan="6" |SAI1_RXD3| rowspan="6" |CPU.HDMI_AUX_NSAI1_RXD3| rowspan="6" |AF17| rowspan="6" | NVCC_3V3|rowspan="6" |I/O| rowspan="6" |Internally used for BOOT mode configuration: can be pulled-up or down depending on Part number composition (boot from eMMC, NAND, etc.)|DALT0|connected with capacitor in seriesSAI1_RX_DATA3|-|ALT1|SAI5_RX_DATA3(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)|-|ALT3|PDM_BIT_STREAM3(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)|-|ALT4|CORESIGHT_TRACE3|-|ALT5|GPIO4_IO05|-|ALT6|SRC_BOOT_CFG3
|-
|J1.107
