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MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table

1,090 bytes added, 15:54, 21 January 2021
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==Connectors and Pinout Table description==
| rowspan="4" |GPIO1_IO00
| rowspan="4" |CPU.GPIO1_IO00
| rowspan="4" |T6AG14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|-
|ALT5
|ANAMIX_REF_CLK_32KCCM_REF_CLK_32K
|-
|ALT6
| rowspan="4" |GPIO1_IO01
| rowspan="4" |CPU.GPIO1_IO01
| rowspan="4" |T7AF14
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|-
|ALT5
|ANAMIX_REF_CLK_25MCCM_REF_CLK_24M
|-
|ALT6
| rowspan="3" |SPDIF_EXT_CLK
| rowspan="3" |CPU.SPDIF_EXT_CLK
| rowspan="3" |E6AF8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO13
| rowspan="3" |CPU.GPIO1_IO13
| rowspan="3" |K6AD9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |Internally used, do not connect
|ALT0
|GPIO1_IO13
|PWM2_OUT
|-
| rowspan="2" |J1.45|VDD_PHY_1V8rowspan="2" |GPIO1_IO11| rowspan="2" |CPU.GPIO1_IO11| rowspan="2" |AC10|rowspan="2" |NVCC_3V3|rowspan="2" |I/O| rowspan="2" |Internally used for ETH CLK enable, do not connect|ALT0|GPIO1_IO11|-|ALT1|USB1_OTG_ID
|-
| rowspan="3" |J1.47
| rowspan="3" |ECSPI2_SCLK
| rowspan="3" |CPU.ECSPI2_SCLK
| rowspan="3" |C5E6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI2_MOSI
| rowspan="3" |CPU.ECSPI2_MOSI
| rowspan="3" |E5B8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO08
| rowspan="3" |CPU.GPIO1_IO08
| rowspan="3" |N7AG10
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|USDHC2_RESET_B
|-
| rowspan="34" |J1.53| rowspan="34" |GPIO1_IO09| rowspan="34" |CPU.GPIO1_IO09| rowspan="34" |M7AF10| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|GPIO1_IO09
|ALT1
|ENET1_1588_EVENT0_OUT
|-
|ALT4
|USDHC3_RESET_B
|-
|ALT5
| rowspan="3" |ECSPI2_MISO
| rowspan="3" |CPU.ECSPI2_MISO
| rowspan="3" |B5A8
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI2_SS0
| rowspan="3" |CPU.ECSPI2_SS0
| rowspan="3" |A5A6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|ALT1
|UART4_RTS_B
(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT5
| rowspan="3" |GPIO1_IO05
| rowspan="3" |CPU.GPIO1_IO05
| rowspan="3" |P7AF12
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
|CCM_PMIC_READY
|-
| rowspan="34" |J1.63| rowspan="34" |I2C2_SCLSAI5_RXD0| rowspan="34" |CPU.I2C2_SCLSAI5_RXD0| rowspan="34" |G7AD18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|I2C2_SCLSAI5_RX_DATA0( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)
|-
|ALT1
|ENET1_1588_EVENT1_INSAI1_TX_DATA2|-|ALT4|PDM_BIT_STREAM0(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4)
|-
|ALT5
|GPIO5_IO16GPIO3_IO21
|-
| rowspan="36" |J1.65| rowspan="36" |I2C2_SDASAI5_RXD1| rowspan="36" |CPU.I2C2_SDASAI5_RXD1| rowspan="36" |F7AC14| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|I2C2_SDASAI5_RX_DATA1(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)
|-
|ALT1
|ENET1_1588_EVENT1_OUTSAI1_TX_DATA3|-|ALT2|SAI1_TX_SYNC(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)|-|ALT3|SAI5_TX_SYNC(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)|-|ALT4|PDM_BIT_STREAM1(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)
|-
|ALT5
|GPIO5_IO17GPIO3_IO22
|-
| rowspan="4" |J1.67
| rowspan="4" |GPIO1_IO06
| rowspan="4" |CPU.GPIO1_IO06
| rowspan="4" |N5AG11
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|CCM_EXT_CLK3
|-
| rowspan="34" |J1.69| rowspan="34" |SAI2_RXC| rowspan="34" |CPU.SAI2_RXC| rowspan="34" |H3AB22| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|SAI2_RX_BCLK
|ALT1
|SAI5_TX_BCLK
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
|-
|ALT4
|UART1_RX
|-
|ALT5
|GPIO4_IO22
|-
| rowspan="36" |J1.71| rowspan="36" |SAI2_RXFS| rowspan="36" |CPU.SAI2_RXFS| rowspan="36" |J4AC19| rowspan="36" |NVCC_3V3| rowspan="36" |I/O| rowspan="36" |
|ALT0
|SAI2_RX_SYNC
|ALT1
|SAI5_TX_SYNC
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
|-
|ALT2
|SAI5_TX_DATA1
|-
|ALT3
|SAI2_RX_DATA1
|-
|ALT4
|UART1_TX
|-
|ALT5
| rowspan="2" |SD2_DATA0
| rowspan="2" |CPU.SD2_DATA0
| rowspan="2" |N22AB23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA1
| rowspan="2" |CPU.SD2_DATA1
| rowspan="2" |N21AB24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA2
| rowspan="2" |CPU.SD2_DATA2
| rowspan="2" |P22V24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_DATA3
| rowspan="2" |CPU.SD2_DATA03
| rowspan="2" |P21V23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_CMD
| rowspan="2" |CPU.SD2_CMD
| rowspan="2" |M22W24
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_CLK
| rowspan="2" |CPU.SD2_CLK
| rowspan="2" |L22W23
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|
|-
| rowspan="34" |J1.89| rowspan="34" |UART3_TXD| rowspan="34" |CPU.UART3_TXD| rowspan="34" |B7D18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |Internally pulled-up to NVCC_3V3
|ALT0
|UART3_TX
|ALT1
|UART1_RTS_B
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)
|-
|ALT2
|USDHC3_VSELECT
|-
|ALT5
|GPIO5_IO27
|-
| rowspan="34" |J1.91| rowspan="34" |UART3_RXD| rowspan="34" |CPU.UART3_RXD| rowspan="34" |A6E18| rowspan="34" |NVCC_3V3| rowspan="34" |I/O| rowspan="34" |
|ALT0
|UART3_RX
|ALT1
|UART1_CTS_B
|-
|ALT2
|USDHC3_RESET_B
|-
|ALT5
|GPIO5_IO26
|-
| rowspan="43" |J1.93| rowspan="43" |UART4_TXDUART1_TXD| rowspan="43" |CPU.UART4_TXDUART1_TXD| rowspan="43" |D7F13| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|UART4_TXUART1_TX
|-
|ALT1
|UART2_RTS_B|-|ALT2|PCIE2_CLKREQ_BECSPI3_MOSI
|-
|ALT5
|GPIO5_IO29GPIO5_IO23
|-
| rowspan="43" |J1.95| rowspan="43" |UART4_RXDUART1_RXD| rowspan="43" |CPU.UART4_RXDUART1_RXD| rowspan="43" |C6E14| rowspan="43" |NVCC_3V3| rowspan="43" |I/O| rowspan="43" |
|ALT0
|UART4_RXUART1_RX
|-
|ALT1
|UART2_CTS_B|-|ALT2|PCIE1_CLKREQ_BECSPI3_SCLK
|-
|ALT5
|GPIO5_IO28GPIO5_IO22
|-
| rowspan="2" |J1.97
| rowspan="2" |SD2_WP
| rowspan="2" |CPU.SD2_WP
| rowspan="2" |M21AA27
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |SD2_RST_B
| rowspan="2" |CPU.SD2_RESET_B
| rowspan="2" |R22AB26
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
|HDMI_DDC_SCL
|CPU.HDMI_DDC_SCL
|R3
|VDD_PHY_1V8
|I/O
|HDMI_DDC_SDA
|CPU.HDMI_DDC_SDA
|P3
|VDD_PHY_1V8
|I/O
|HDMI_AUX_N
|CPU.HDMI_AUX_N
|V2
| -
|D
|HDMI_AUX_P
|CPU.HDMI_AUX_P
|V1
| -
|D
|HDMI_TX_M_LN_3
|CPU.HDMI_TX_M_LN_3
|M2
| -
|D
|HDMI_TX_P_LN_3
|CPU.HDMI_TX_P_LN_3
|M1
| -
|D
|HDMI_TX_M_LN_0
|CPU.HDMI_TX_M_LN_0
|T2
| -
|D
|HDMI_TX_P_LN_0
|CPU.HDMI_TX_P_LN_0
|T1
| -
|D
|HDMI_TX_M_LN_1
|CPU.HDMI_TX_M_LN_1
|U1
| -
|D
|HDMI_TX_P_LN_1
|CPU.HDMI_TX_P_LN_1
|U2
| -
|D
|HDMI_TX_M_LN_2
|CPU.HDMI_TX_M_LN_2
|N1
| -
|D
|HDMI_TX_P_LN_2
|CPU.HDMI_TX_P_LN_2
|N2
| -
|D
|HDMI_CEC
|CPU.HDMI_CEC
|W3
|VDD_PHY_1V8
|I/O
|HDMI_HPD
|CPU.HDMI_HPD
|W2
|VDD_PHY_1V8
|I/O
| rowspan="2" |SD2_CD_B
| rowspan="2" |CPU.SD2_CD_B
| rowspan="2" |L21
| rowspan="2" |NVCC_3V3
| rowspan="2" |I/O
| rowspan="3" |ECSPI1_SS0
| rowspan="3" |CPU.ECSPI1_SS0
| rowspan="3" |D4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI1_SCLK
| rowspan="3" |CPU.ECSPI1_SCLK
| rowspan="3" |D5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI1_MISO
| rowspan="3" |CPU.ECSPI1_MISO
| rowspan="3" |B4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO03
| rowspan="3" |CPU.GPIO1_IO03
| rowspan="3" |P4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART2_TXD
| rowspan="3" |CPU.UART2_TXD
| rowspan="3" |D6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART2_RXD
| rowspan="3" |CPU.UART2_RXD
| rowspan="3" |B6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART1_TXD
| rowspan="3" |CPU.UART1_TXD
| rowspan="3" |A7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART1_RXD
| rowspan="3" |CPU.UART1_RXD
| rowspan="3" |C7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |ECSPI1_MOSI
| rowspan="3" |CPU.ECSPI1_MOSI
| rowspan="3" |A4
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="4" |GPIO1_IO14
| rowspan="4" |CPU.GPIO1_IO14
| rowspan="4" |K7
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="3" |GPIO1_IO04
| rowspan="3" |CPU.GPIO1_IO04
| rowspan="3" |P5
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |GPIO1_IO12
| rowspan="3" |CPU.GPIO1_IO12
| rowspan="3" |L7
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
U0005
a000298_approval, dave_user
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