SBC Axel SBC/Interfaces and Connectors/LVDS
History | |||
---|---|---|---|
ID# | Issue Date | Notes | |
22/09/2021 | First DESK release |
Contents
LVDS[edit | edit source]
Description[edit | edit source]
SBCX provides two LVDS interfaces, LVDS0 and LVDS1.
- J8 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector
- J9 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector
Signals[edit | edit source]
The following tables describes the interface signals
LVDS0[edit | edit source]
Pin# | SOM Pin# | Pin name | Pin function | Pin Notes |
---|---|---|---|---|
1, 2 | - | 3.3V_LCD0 | 3.3 V | |
3, 4, 7, 10,
13, 16, 19 |
- | DGND | Ground | |
5 | J10.137 | LVDS0_TX0_N | LVDS Data 0 - | |
6 | J10.139 | LVDS0_TX0_P | LVDS Data 0 + | |
8 | J10.141 | LVDS0_TX1_N | LVDS Data 1 - | |
9 | J10.143 | LVDS0_TX1_P | LVDS Data 1 + | |
11 | J10.145 | LVDS0_TX2_N | LVDS Data 2 - | |
12 | J10.147 | LVDS0_TX2_P | LVDS Data 2 + | |
14 | J10.133 | LVDS0_CLK_N | LVDS Clock - | |
15 | J10.135 | LVDS0_CLK_P | LVDS Clock + | |
17 | J10.149 | LVDS0_P17 | Mount options | LVDS0_TX3_N option |
18 | J10.151 | LVDS0_P18 | Mount options | LVDS0_TX3_P option |
20 | J10.46 | LVDS0_P20 | Mount options | GND or PWM (J10.46) option |
LVDS1[edit | edit source]
Pin# | SOM Pin# | Pin name | Pin function | Pin Notes |
---|---|---|---|---|
1, 2 | - | 3.3V_LCD0 | 3.3 V | |
3, 4, 7, 10,
13, 16, 19 |
- | DGND | Ground | |
5 | J10.159 | LVDS1_TX0_N | LVDS Data 0 - | |
6 | J10.161 | LVDS1_TX0_P | LVDS Data 0 + | |
8 | J10.163 | LVDS1_TX1_N | LVDS Data 1 - | |
9 | J10.165 | LVDS1_TX1_P | LVDS Data 1 + | |
11 | J10.167 | LVDS1_TX2_N | LVDS Data 2 - | |
12 | J10.169 | LVDS1_TX2_P | LVDS Data 2 + | |
14 | J10.155 | LVDS1_CLK_N | LVDS Clock - | |
15 | J10.157 | LVDS1_CLK_P | LVDS Clock + | |
17 | J10.171 | LVDS1_P17 | Mount options | LVDS1_TX3_N option |
18 | J10.173 | LVDS1_P18 | Mount options | LVDS1_TX3_P option |
20 | J10.46 | LVDS1_P20 | Mount options | GND or PWM (J10.46) option |
Device mapping[edit | edit source]
- LVDS0 is mapped to
/dev/fb0
device in Linux - LVDS1 is mapped to the corresponding device driver in Linux, depending on the
ldb
peripheral configuration in the device tree. The default value is disabled but can be mapped to/dev/fb2
(second and independent LCD panel) or can be the second LVDs channel for a dual-channel LCD panel configuration (like a 1920x1080 DUAL LVDS channel LCD panel)
Power sequence[edit | edit source]
Most of the LCD panels have many supplies and need a specific timing to power the rails and start the signals.
The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.
The following sections describe the available rails:
3V3_LCD[edit | edit source]
The most common voltage to supply the LCD panel internal logic:
- rail 3V3_LCD0 is enabled by
GPIO1_IO00
- rail 3V3_LCD1 is enabled by
GPIO1_IO02
5V_LCD[edit | edit source]
The most common voltage to supply the LCD panel backlight:
- rail 5V_LCD0 is enabled by
SD3_DATA1
- rail 5V_LCD1 is enabled by
SD3_DATA0
Device usage[edit | edit source]
The associated framebuffer device is accessed in Linux through the standard graphic access.