Power consumption (BoraLite)

Info Box Applies to BORA Lite

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	THIS PAGE IS OBSOLETE, DON'T USE IT AS REFERENCE
The new documentation is available here: BORA_Lite_SOM/BORA_Lite_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Power_consumption

Introduction

Providing maximum power consumption of a system-on-module (SOM for short) is virtually impossible because it is extremely hard to define the worst case. This is even more true in case of BORA Lite, where this is affected by the software running on Processing System (PS) side and the Programmable Logic (PL) configuration.

For this reason, several real use cases have been considered rather than indicating a theoretical maximum power consumption value that would be useless for the majority of system integrators, because it likely would lead to an oversized power supply unit.

Again, it is worth remembering that BORA Lite platform is so flexible that is practically impossible to test for all possible configurations and applications on the market. The use cases here presented should cover most of the real-world scenarios. However, actual customer application might require more power than values reported here. Generally speaking, application-specific requirements have to be taken into consideration in order to size the power supply unit and to implement thermal management properly.

The following sections describe in detail the testbeds that have been used. All of them make use of a specific FPGA bistream that has been developed to perform stress tests on BORA Lite platforms [1]. These tests have been conducted in a climatic chamber that allows setting environment temperature surrounding DUT, denoted in the rest of the document as Tamb. Tj denotes Zynq's junction temperature instead.

FPGA bitstream - that in turn is built upon this core - allocates most of FPGA resources. All of them are clocked by one clock signal whose frequency is selectable by the PS at runtime. This allows to flexibly change DUT current absorption and, consequently, the heat it generates.

Configuration #1

Testbed

Measurements have been performed on the following platform:

• BoraLite SOM: DBTD4111I0R
  • this model is based on Zynq XC7Z020-1I (Tj: -40°C / +100°C)
• carrier board: BoraXEVB
• processor frequency: 667 MHz
• FPGA frequency
  • 1 MHz (Tamb = +85°C)
  • 140 MHz (Tamb = +-40°C)
• U-Boot: 2017.01-belk-4.1.1 (Jan 08 2020 - 16:52:16) [belk-4.1.1]
• Linux kernel: 4.9.0-belk-4.1.0-xilinx #1 SMP PREEMPT Tue Dec 24 11:34:28 CET 2019 armv7l armv7l armv7l GNU/Linux
• root file system mounted over Gigabit Ethernet link.

Please note that, when Tamb has been set to +85°C, the Bora SOM has been coupled to a passive heat sink to prevent exceeding maximum Zynq's junction temperature.

At the application level, PS executes concurrently several tasks including:

• two instances of burnCortexA9
• endless loop of many MTD tests on NAND device
• periodic reading of Zynq's ADCs
• periodic reading of voltage/current probe (Texas Instruments INA226) connected to the SOM's power rail
• one instance of memtester, exercising 50 MByte of SDRAM
• endless loop of writing/reading/verifying operations on microSD card
• endless loop of iperf test through ethernet
• endless loop of writing/reading/verifying operations on memory stick connected to the USB port.

Results

• Tamb: temperature of the ambient surrounding the DUT
• Tj_max: maximum Zynq's junction temperature measured during the test
• P_max: maximum power absorption of Bora SOM

Tamb [°C]	Tj_max [°C]	FPGA clock frequency [MHz]	P_max [W]
85	116.4 [1]	1	7.9
-40	81.9	140	7.2

[1] In spite of the use of heat sink, this value exceeds maximum valued declared by the manufacturer. This is acceptable in case of stress tests, where it is possible that parts of the DUT get damaged.