Power Supply Unit (PSU) and recommended power-up sequence
Implementing correct power-up sequence for Zynq-based system is not a trivial task because several power rails are involved. Bora SOM simplifies this task and embeds all the needed circuitry. The following picture shows a simplified block diagram of power supply subsystem.
The recommended power-up sequence is:
- main power supply rail (3.3VIN) ramps up
- carrier board circuitry raises CB_PWR_GOOD; this indicates 3.3VIN rail is stable (1)
- Bora's PSU enables and sequences DC/DC regulators to turn circuitry on
- BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa).
Please note that FPGA Bank 13 and FPGA Bank 35 of the PL must be powered by carrier board even if they are not used to implement any function. Two dedicated power rails are available for this purpose (VDDIO_BANK35 and VDDIO_BANK13), offering the system designer the freedom to select the I/O voltage of these two banks. The power rails of both banks are enabled by the BOARD_PGOOD signal and are connected to the I/O power supply rail provided by the carrier board. Bank 13 and bank 35 are High Range (HR), hence the 1.2V - 3.3V voltage range is supported. For more details please refer to . The state of FPGA I/Os prior to configuration is influenced by PUD_C signal as well. For this reason reading of  and  is also recommended.
Bora's PSU is designed to be robust against misbehaving power rails. However, the recommended power-on ramp for core and I/O supplies ranges from 1 to 6 V/ms.
N.B.: Regarding power off, it is recommended taht I/O supply is turned off before core supply.
(1) This step is not mandatory and CB_PWR_GOOD can be left floating. CB_PWR_GOOD is provided to prevent, if necessary, Bora's PSU to turn on during ramp of carrier board 3.3VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches during ramp-up.
XCN15034 and power-off sequence
On 29th September 2015 Xilinx released a Product Change Notice indicating new power on/off requirements about Zynq components. A specific analysis has been undertaken with the help of Xilinx technical support to verify the compliance of Bora with respect to the new requirements. This activity has led to the following recommendation: in order to prevent situations that might not fulfill such requirements, 3.3VIN off ramp speed must not exceed 50 V/ms.For more details about this matter, please refer to AR #65240 and XCN15034.
- Xilinx, DS187 Zynq-7000 All Programmable SoC (Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics