ONDA SOM/ONDA Hardware/Peripherals/eMMC

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History
Issue Date Notes
2026/03/16 First documentation release


Peripheral eMMC[edit | edit source]

The second SD/SDIO controller is used for interfacing the on-board eMMC and can operate at the maximum clock rate in Standard mode (25 MHz), High-speed SDR mode (50 MHz), High-Speed DDR mode (50 MHz), HS200 mode (200 MHz). The SD/SDIO controller supports MMC4.51.

The following table describes the external ONDA interface signals for the eMMC interface (MIO bank 500, pins PS_MIO[13:21]):

Pin name Conn. pin Function Notes
PS_MIO13_500 - eMMC D0 -
PS_MIO14_500 - eMMC D1 -
PS_MIO15_500 - eMMC D2 -
PS_MIO16_500 - eMMC D3 -
PS_MIO17_500 - eMMC D4 -
PS_MIO18_500 - eMMC D5 -
PS_MIO19_500 - eMMC D6 -
PS_MIO20_500 - eMMC D7 -
PS_MIO21_500 - eMMC CMD -
PS_MIO22_500 - eMMC CLK -