ONDA SOM/ONDA Hardware/Peripherals/QSPI
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Contents
Peripheral QSPI[edit | edit source]
The two Quad-SPI controllers are configured to operate in a dual SS parallel configuration with two NOR SPI memory devices (bootable storage).
The controller supports up to two SPI flash memories operating in parallel: in this configuration, the maximum addressable SPI flash memory is 32 MB (25-bit address).
The following table describes the interface signals (MIO bank 500, pins PS_MIO[00:12]):
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| PS_MIO00_500 | - | QSPI0 serial clock | NOR0 SCK |
| PS_MIO01_500 | - | QSPI0 IO1 | NOR0 IO pin 1 |
| PS_MIO02_500 | - | QSPI0 IO2 | NOR0 IO pin 2 |
| PS_MIO03_500 | - | QSPI0 IO3 | NOR0 IO pin 3 |
| PS_MIO04_500 | - | QSPI0 IO0 | NOR0 IO pin 0 |
| PS_MIO05_500 | - | QSPI0 chip select | NOR0 CS# |
| PS_MIO07_500 | - | QSPI1 chip select | NOR1 CS# |
| PS_MIO08_500 | - | QSPI1 IO0 | NOR1 IO pin 0 |
| PS_MIO09_500 | - | QSPI1 IO1 | NOR1 IO pin 1 |
| PS_MIO010_500 | - | QSPI1 IO2 | NOR1 IO pin 2 |
| PS_MIO011_500 | - | QSPI1 IO3 | NOR1 IO pin 3 |
| PS_MIO012_500 | - | QSPI1 serial clock | NOR1 SCK |
