ONDA Plus SOM/ONDA Plus Hardware/Peripherals/Ethernet
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Contents
Peripheral Ethernet[edit | edit source]
On-board gigabit Ethernet PHY (Microchip LAN8830) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the GEM3 Gigabit Ethernet Controller through the RGMII interface on MIO bank 502, pins PS_MIO[64:77]. For further details (eg: connection and selection of the magnetics), please refer to the Microchip LAN8830 datasheet.
The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| ETH_TXRX0_N | J1.B49 | Media Dependent Interface[0], negative pin | - |
| ETH_TXRX0_P | J1.B50 | Media Dependent Interface[0], positive pin | - |
| ETH_TXRX1_N | J1.B52 | Media Dependent Interface[1], negative pin | - |
| ETH_TXRX1_P | J1.B53 | Media Dependent Interface[1], positive pin | - |
| ETH_TXRX2_N | J1.B55 | Media Dependent Interface[2], negative pin | - |
| ETH_TXRX2_P | J1.B56 | Media Dependent Interface[2], positive pin | - |
| ETH_TXRX3_N | J1.B58 | Media Dependent Interface[3], negative pin | - |
| ETH_TXRX3_P | J1.B59 | Media Dependent Interface[3], positive pin | - |
| PS_MIO76_502 | - | ETH_MDC Management Data Clock input | - |
| PS_MIO77_502 | - | ETH_MDIO Management Data Input/Output | - |
| ETH_INTn | J1.B41 | Ethernet PHY interrupt | - |
| ETH_RSTn | J2.B42 | Ethernet reset interrupt | PHY reset is also driven by RSTn SOM_PER_RSTn signal.
See Reset scheme and control signals page for more information |
| ETH_LED1 | J1.B47 | Activity LED | - |
| ETH_LED2 | J1.B46 | Link LED | - |
| ETH_LED3 | J1.B45 | LED3 | - |
| ETH_LED4 | J1.B44 | LED4 | - |
