DESK-RZ-L/Peripherals/PWM
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Contents
Peripheral PWM[edit | edit source]
Configuration[edit | edit source]
These peripheral(s) can only be used with the following ConfigID(s) (see the associated BOM):
| ConfigID | Note |
|---|---|
| 2002 | PWM is used for display backlight & two pins on CN24 |
| 2003 | All PWM channels are required for motors |
Device tree configuration[edit | edit source]
Below is an example of a device tree configuration used on a standard DAVE kit for the DSAB EVK.
From rzt2h-eb23-cb2002.dts:
...
&gpt00_3 {
pinctrl-0 = <&gpt00_3_pins>;
pinctrl-names = "default";
channel = "channel_B";
status = "okay";
};
&gpt02_0 {
pinctrl-0 = <&gpt02_0_pins>;
pinctrl-names = "default";
channel = "both_AB";
status = "okay";
};
...
&pinctrl {
...
gpt00_3_pins: gpt00 {
pinmux = <RZT2H_PORT_PINMUX(0, 7, 0x9)>; /* P00_7 GTIOC00_3B */
};
gpt02_0_pins: gpt02 {
pinmux = <RZT2H_PORT_PINMUX(2, 5, 0x9)>, /* P02_5 GTIOC02_0A | B_AB10 AD11 */
<RZT2H_PORT_PINMUX(2, 6, 0x9)>; /* P02_6 GTIOC02_0B | B_AB8 AD9 */
};
...
};
Accessing the peripheral[edit | edit source]
Linux[edit | edit source]
... [ 0.384899] gpt-rzg2l 90002300.gpt00_3: RZ/G2L GPT Driver probed [ 0.385742] gpt-rzg2l 90004000.gpt02_0: RZ/G2L GPT Driver probed [ 1054.619013] gpt-rzg2l 90004000.gpt02_0: In both channel A and B output please set duty cycle via buff [ 1070.343009] gpt-rzg2l 90004000.gpt02_0: In both channel A and B output please set duty cycle via buff [ 1074.775003] gpt-rzg2l 90004000.gpt02_0: In both channel A and B output please set duty cycle via buff ...
The GPT cell gpt00_3 is dedicated to the backlight and cannot be used directly as a PWM; see the LCD display page.
The cell gpt02_0 is usable as a PWM. By default, the channels are set to both_AB; as reported in dmesg, the duty cycle must be set differently.
Example of using a single PWM (switching to single-channel mode):
echo 0 > /sys/class/pwm/pwmchip1/export echo channel_B > /sys/class/pwm/pwmchip1/device/gpt_channel
PWM configuration and enablement:
echo 1000000 > /sys/class/pwm/pwmchip1/pwm0/period echo 500000 > /sys/class/pwm/pwmchip1/pwm0/duty_cycle echo 1 > /sys/class/pwm/pwmchip1/pwm0/enable
The pin controlled in this example is CN24.28.
Channel A is routed to pin J54.27, next to the pin shown in the image.
