DESK-RZ-L/Peripherals/PCIe
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Contents
Peripheral PCI express[edit | edit source]
The PCIe bus is available; see details in RZ/T2H and RZ/N2H User’s Manual – Hardware, section 56 PCI Express 3.0 Interface (PCIe).
The PCIe bus can be configured in the following modes:
- 1 lane with 2 channels
- 2 lanes with 1 channel each
The EVK uses the second configuration (2 lanes with 1 channel each).
Warning: If no device is connected at boot, there will be a delay while the PCIe block attempts to communicate with a device until a timeout occurs. If a device is detected during the boot, there will be no interruptions or pauses.
Configuration[edit | edit source]
These peripheral(s) can only be used with the following ConfigID(s) (see the associated BOM):
| ConfigID | Note |
|---|---|
| 2002 | - |
| 2003 | - |
Device tree configuration[edit | edit source]
Below is an example of a device tree configuration used on ZERO Evaluation Kit.
From rzt2h-eb23-cb2003.dtsi:
...
&pcie0 {
pcie-lane = <1>;
num-lanes = <1>;
status = "okay";
};
&pcie1 {
pcie-lane = <1>;
num-lanes = <1>;
status = "okay";
};
...
Linux[edit | edit source]
In the example shown, the following devices are connected to the 2 PCIe lanes:
... [ 0.228411] gpio-337 (pcie_rstout0): hogged as output/high [ 0.228463] gpio-269 (pcie_rstout1): hogged as output/high [ 0.375659] rzt2h-pcie 92100000.pcie: host bridge /soc/pcie@92100000 ranges: [ 0.375702] rzt2h-pcie 92100000.pcie: Parsing ranges property... [ 0.375729] rzt2h-pcie 92100000.pcie: MEM 0x0400000000..0x040fffffff -> 0x00a0000000 [ 0.375769] rzt2h-pcie 92100000.pcie: Parsing dma-ranges property... [ 0.375806] rzt2h-pcie 92100000.pcie: IB MEM 0x00c4000000..0x00ffffffff -> 0x00c4000000 [ 0.375856] rzt2h-pcie 92100000.pcie: IB MEM 0x0240000000..0x03ffffffff -> 0x0240000000 [ 0.376362] rzt2h-pcie 92100000.pcie: pcie set lane config: num-lanes=1, val=0x300 [ 0.462183] rzt2h-pcie 92100000.pcie: PCIe Linx status [0x106]n [ 0.462214] rzt2h-pcie 92100000.pcie: PCIe x1: link up Lane number [ 0.464427] rzt2h-pcie 92100000.pcie: Current link speed is 5.0 GT/s [ 0.464615] rzt2h-pcie 92100000.pcie: PCI host bridge to bus 0000:00 [ 0.481984] rzt2h-pcie 92110000.pcie: host bridge /soc/pcie@92110000 ranges: [ 0.482024] rzt2h-pcie 92110000.pcie: Parsing ranges property... [ 0.482051] rzt2h-pcie 92110000.pcie: MEM 0x0600000000..0x060fffffff -> 0x00b0000000 [ 0.482090] rzt2h-pcie 92110000.pcie: Parsing dma-ranges property... [ 0.482127] rzt2h-pcie 92110000.pcie: IB MEM 0x00c4000000..0x00ffffffff -> 0x00c4000000 [ 0.482200] rzt2h-pcie 92110000.pcie: IB MEM 0x0240000000..0x03ffffffff -> 0x0240000000 [ 0.482553] rzt2h-pcie 92110000.pcie: pcie set lane config: num-lanes=1, val=0x300 [ 0.566175] rzt2h-pcie 92110000.pcie: PCIe Linx status [0x102]n [ 0.566205] rzt2h-pcie 92110000.pcie: PCIe x1: link up Lane number [ 0.567838] rzt2h-pcie 92110000.pcie: PCI host bridge to bus 0001:00 ... root@desk-t2h-usd-devel:~# lspci 0000:00:00.0 Unassigned class [ff04]: Renesas Technology Corp. Device 1135 0000:01:00.0 USB controller: Renesas Technology Corp. uPD720202 USB 3.0 Host Controller (rev 02) 0001:00:00.0 Unassigned class [ff04]: Renesas Technology Corp. Device 1135 0001:01:00.0 Ethernet controller: Marvell Technology Group Ltd. Device 2b42 (rev 11)
Note[edit | edit source]
The clock signal must be requested by the PCIe devices. If a device is not found or recognized, first check whether the clock is present. If the clock is missing, the inserted device probably does not drive the Clock Request pin. Manual intervention is possible via test points or components:
- TP140 – to handle the Clock Request for the J15 PCIe connector
- D46.1 (white dot marks pin 1) – to handle the Clock Request for the J18 M.2 connector
