DESK-RZ-L/Peripherals/Ethernet
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Contents
Peripheral Ethernet[edit | edit source]
There are multiple Ethernet interfaces available; see RZ/T2H and RZ/N2H User’s Manual – Hardware, section 27 Ethernet Subsystem.
The device provides three GMAC instances, allowing up to three independent Ethernet interfaces. A fourth interface can be used together with the others to achieve an EtherCAT or switch configuration.
As described in the user manual, section 27.3.2, the possible configurations are:
| Mode | Interface 0 | Interface 1 | Interface 2 | Interface 3 |
|---|---|---|---|---|
| 000b | ETHSW Port 0 | ETHSW Port 1 | ETHSW Port 2 | GMAC1 |
| 001b | ESC Port 0 | ESC Port 1 | GMAC2 | GMAC1 |
| 010b | ESC Port 0 | ESC Port 1 | ETHSW Port 2 | GMAC1 |
| 011b | ESC Port 0 | ESC Port 1 | ESC Port 2 | GMAC1 |
| 100b | ETHSW Port 0 | ESC Port 1 | ESC Port 2 | GMAC1 |
| 101b | ETHSW Port 0 | ESC Port 1 | ETHSW Port 2 | GMAC1 |
| 110b | ETHSW Port 0 | ETHSW Port 1 | GMAC2 | GMAC1 |
| 111b | GMAC0 | GMAC1 | GMAC2 | — |
The default/basic setup is:
| Mode | Interface 0 | Interface 1 | Interface 2 | Interface 3 |
|---|---|---|---|---|
| 111b | GMAC0 | GMAC1 | GMAC2 | — |
The Ethernet PHYs are not present on the SoM; they must be provided on the carrier board.
The three Ethernet interfaces share the same MDIO bus. This bus is defined in the GMAC0 block; see the DTS in the following section.
The fourth Ethernet PHY is present but not used in the current configuration and is connected to a different MDIO bus.
The address/mapping is as follows:
| Interface | GMAC | MDIO Bus | Address |
|---|---|---|---|
| ETH_A | gmac0 | GMAC0 | 0 |
| ETH_B | gmac1 | GMAC0 | 1 |
| ETH_C | gmac2 | GMAC0 | 2 |
| ETH_D | — | ETHSW | 3 |
Configuration[edit | edit source]
These peripheral(s) can only be used with the following ConfigID(s) (see the associated BOM):
| ConfigID | Note |
|---|---|
| 2002 | ETH_D pins connected to the Ethernet PHY |
| 2003 | Ignore references to the ETH_D port, as the pins are used for the motors |
Device tree configuration[edit | edit source]
Below is an example of a device tree configuration used on a standard DAVE kit for the DSAB EVK.
The Ethernet PHY reset pins are controlled by a GPIO expander (exp_2) connected on the i2c_0 bus.
From rzt2h-eb23-cb2003.dtsi :
// ETH SubSystem
ðss {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pins_refclk>,
<ð0_pins>, // ETH_A
<ð1_pins>, // ETH_B
<ð2_pins>; // ETH_C
//renesas,ethss-switch-portmanagement = <ETHSS_GMAC0_PORT>;
ethsw_pulse_gen_timer = <0>; /* Pulse generator use ETHSW timer 0 */
};
// ETH_A
&mii_conv0 {
renesas,ethss-port = <ETHSS_GMAC0_PORT>;
status = "okay";
};
// ETH_B
&mii_conv1 {
renesas,ethss-port = <ETHSS_GMAC1_PORT>;
status = "okay";
};
// ETH_C
&mii_conv2 {
renesas,ethss-port = <ETHSS_GMAC2_PORT>;
status = "okay";
};
// ETH_A
&gmac0 {
status = "okay";
ethss-handle = <ðss>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
pcs-handle = <&mii_conv0>;
phy-reset-gpios = <&exp_2 4 GPIO_ACTIVE_HIGH>;
enable-time-based-scheduling;
snps,force_thresh_dma_mode;
snps,tx_threshold = <128>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
pinctrl-0 = <&mdio_b>;
pinctrl-names = "default";
mdio {
clock-frequency = <2500000>;
#address-cells = <1>;
#size-cells = <0>;
// ETH A
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0772";
reg = <0>;
phy-mode = "rgmii-id";
vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-combine-disable;
};
// ETH B
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id0007.0772";
reg = <1>;
phy-mode = "rgmii-id";
vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-combine-disable;
};
// ETH C
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id0007.0772";
reg = <2>;
phy-mode = "rgmii-id";
vsc8531,led-0-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-1-combine-disable;
};
};
};
// ETH_B
&gmac1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
pcs-handle = <&mii_conv1>;
status = "okay";
ethss-handle = <ðss>;
phy-reset-gpios = <&exp_2 5 GPIO_ACTIVE_HIGH>;
enable-time-based-scheduling;
snps,force_thresh_dma_mode;
snps,tx_threshold = <128>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
};
// ETH_C
&gmac2 {
phy-handle = <&phy2>;
phy-mode = "rgmii-id";
pcs-handle = <&mii_conv2>;
status = "okay";
ethss-handle = <ðss>;
phy-reset-gpios = <&exp_2 15 GPIO_ACTIVE_HIGH>;
enable-time-based-scheduling;
snps,force_thresh_dma_mode;
snps,tx_threshold = <128>;
snps,mtl-tx-config = <&mtl_tx_setup>;
snps,mtl-rx-config = <&mtl_rx_setup>;
};
// I2C A (need to use eth reset)
&i2c0 {
clock-frequency = <100000>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
...
// U15
exp_2: gpio_exp_2@76 {
compatible = "ti,tca9539";
reg = <0x76>;
vcc-supply = <®_exp_3p3v>;
#address-cells = <1>;
#size-cells = <0>;
#gpio-cells = <2>;
gpio-controller;
pinctrl-names = "default";
pinctrl-0 = <&tca6424_2_pins>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 62 GPIO_ACTIVE_LOW>;
};
};
...
&pinctrl {
...
pins_refclk: pins_refclk {
pinmux = <RZT2H_PORT_PINMUX(21, 7, 0x02)>, /* P21_7 ETH0_REFCLK | B_N16 D17 */
<RZT2H_PORT_PINMUX(26, 4, 0x02)>, /* P26_4 ETH1_REFCLK | B_M2 C25 */
<RZT2H_PORT_PINMUX(31, 0, 0x02)>, /* P31_0 ETH2_REFCLK | B_R34 L24 */
<RZT2H_PORT_PINMUX(34, 6, 0x02)>; /* P34_6 ETH3_REFCLK | B_AM2 R23 */
};
eth0_pins: ethss_0 {
pinmux = <RZT2H_PORT_PINMUX(20, 0, 0x0F)>, /* P20_0 ETH0_TXCLK | B_J15 A18 */
<RZT2H_PORT_PINMUX(20, 1, 0x0F)>, /* P20_1 ETH0_TXD0 | B_H15 A17 */
<RZT2H_PORT_PINMUX(20, 2, 0x0F)>, /* P20_2 ETH0_TXD1 | B_G15 E17 */
<RZT2H_PORT_PINMUX(20, 3, 0x0F)>, /* P20_3 ETH0_TXD2 | B_H16 C17 */
<RZT2H_PORT_PINMUX(20, 4, 0x0F)>, /* P20_4 ETH0_TXD3 | B_G16 F17 */
<RZT2H_PORT_PINMUX(20, 5, 0x0F)>, /* P20_5 ETH0_TXEN | B_K16 B17 */
<RZT2H_PORT_PINMUX(20, 6, 0x0F)>, /* P20_6 ETH0_RXCLK | B_R15 C18 */
<RZT2H_PORT_PINMUX(20, 7, 0x0F)>, /* P20_7 ETH0_RXD0 | B_K15 D18 */
<RZT2H_PORT_PINMUX(21, 0, 0x0F)>, /* P21_0 ETH0_RXD1 | B_L15 E18 */
<RZT2H_PORT_PINMUX(21, 1, 0x0F)>, /* P21_1 ETH0_RXD2 | B_N15 G17 */
<RZT2H_PORT_PINMUX(21, 2, 0x0F)>, /* P21_2 ETH0_RXD3 | B_P15 B19 */
<RZT2H_PORT_PINMUX(21, 3, 0x0F)>, /* P21_3 ETH0_RXDV | B_M15 A19 */
<RZT2H_PORT_PINMUX(22, 2, 0x0F)>, /* P22_2 ETH0_RXER | B_L16 E22 */
<RZT2H_PORT_PINMUX(22, 3, 0x0F)>, /* P22_3 ETH0_CRS | B_E16 F20 */
<RZT2H_PORT_PINMUX(22, 4, 0x0F)>; /* P22_4 ETH0_COL | B_F15 E20 */
input-schmitt-disable;
slew-rate = <1>;
drive-strength = <3>;
};
eth1_pins: ethss_1 {
pinmux = <RZT2H_PORT_PINMUX(24, 5, 0x0F)>, /* P24_5 ETH1_TXCLK | B_H1 C24 */
<RZT2H_PORT_PINMUX(24, 6, 0x0F)>, /* P24_6 ETH1_TXD0 | B_G1 A23 */
<RZT2H_PORT_PINMUX(24, 7, 0x0F)>, /* P24_7 ETH1_TXD1 | B_F1 C23 */
<RZT2H_PORT_PINMUX(25, 0, 0x0F)>, /* P25_0 ETH1_TXD2 | B_G2 B25 */
<RZT2H_PORT_PINMUX(25, 1, 0x0F)>, /* P25_1 ETH1_TXD3 | B_F2 A26 */
<RZT2H_PORT_PINMUX(25, 2, 0x0F)>, /* P25_2 ETH1_TXEN | B_J2 A24 */
<RZT2H_PORT_PINMUX(25, 3, 0x0F)>, /* P25_3 ETH1_RXCLK | B_P1 B26 */
<RZT2H_PORT_PINMUX(25, 4, 0x0F)>, /* P25_4 ETH1_RXD0 | B_J1 E23 */
<RZT2H_PORT_PINMUX(25, 5, 0x0F)>, /* P25_5 ETH1_RXD1 | B_K1 F23 */
<RZT2H_PORT_PINMUX(25, 6, 0x0F)>, /* P25_6 ETH1_RXD2 | B_M1 D23 */
<RZT2H_PORT_PINMUX(25, 7, 0x0F)>, /* P25_7 ETH1_RXD3 | B_N1 E24 */
<RZT2H_PORT_PINMUX(26, 0, 0x0F)>, /* P26_0 ETH1_RXDV | B_L1 D25 */
<RZT2H_PORT_PINMUX(26, 7, 0x0F)>, /* P26_7 ETH1_RXER | B_L16 H22 */
<RZT2H_PORT_PINMUX(27, 0, 0x0F)>, /* P27_0 ETH1_CRS | B_E16 G23 */
<RZT2H_PORT_PINMUX(27, 1, 0x0F)>; /* P27_1 ETH1_COL | B_F15 G24 */
input-schmitt-disable;
slew-rate = <1>;
drive-strength = <3>;
};
eth2_pins: ethss_2 {
pinmux = <RZT2H_PORT_PINMUX(29, 1, 0x0F)>, /* P29_1 ETH2_TXCLK | B_N35 J25 */
<RZT2H_PORT_PINMUX(29, 2, 0x0F)>, /* P29_2 ETH2_TXD0 | B_Y35 K23 */
<RZT2H_PORT_PINMUX(29, 3, 0x0F)>, /* P29_3 ETH2_TXD1 | B_AA35 H27 */
<RZT2H_PORT_PINMUX(29, 4, 0x0F)>, /* P29_4 ETH2_TXD2 | B_Y34 L22 */
<RZT2H_PORT_PINMUX(29, 5, 0x0F)>, /* P29_5 ETH2_TXD3 | B_AA34 L23 */
<RZT2H_PORT_PINMUX(29, 6, 0x0F)>, /* P29_6 ETH2_TXEN | B_V34 J23 */
<RZT2H_PORT_PINMUX(29, 7, 0x0F)>, /* P29_7 ETH2_RXCLK | B_W35 L25 */
<RZT2H_PORT_PINMUX(30, 0, 0x0F)>, /* P30_0 ETH2_RXD0 | B_V35 K27 */
<RZT2H_PORT_PINMUX(30, 1, 0x0F)>, /* P30_1 ETH2_RXD1 | B_U35 K25 */
<RZT2H_PORT_PINMUX(30, 2, 0x0F)>, /* P30_2 ETH2_RXD2 | B_R35 L26 */
<RZT2H_PORT_PINMUX(30, 3, 0x0F)>, /* P30_3 ETH2_RXD3 | B_P35 J27 */
<RZT2H_PORT_PINMUX(30, 4, 0x0F)>, /* P30_4 ETH2_RXDV | B_T35 K24 */
<RZT2H_PORT_PINMUX(31, 3, 0x0F)>, /* P31_3 ETH2_RXER | B_L16 E22 */
<RZT2H_PORT_PINMUX(31, 4, 0x0F)>, /* P31_4 ETH2_CRS | B_E16 F20 */
<RZT2H_PORT_PINMUX(31, 5, 0x0F)>; /* P31_5 ETH2_COL | B_F15 E20 */
input-schmitt-disable;
slew-rate = <1>;
drive-strength = <3>;
};
mdio_b: mdio_pins {
pinmux = <RZT2H_PORT_PINMUX(21, 4, 0x10)>, /* P21_4 GMAC0_MDC | B_C6 C19 */
<RZT2H_PORT_PINMUX(21, 5, 0x10)>; /* P21_5 GMAC0_MDIO | B_C7 G16 */
};
i2c0_pins: i2c0 {
pinmux = <RZT2H_PORT_PINMUX(2, 3, 0x17)>, /* P02_3 SDA | B_AA15 AF12 */
<RZT2H_PORT_PINMUX(2, 4, 0x17)>; /* P02_4 SCL | B_AA16 AE12 */
};
...
};
Accessing the peripheral[edit | edit source]
The interfaces are mapped as described in the aliases section of the DTS:
/ {
...
aliases {
...
i2c0 = &i2c0;
eth0 = &gmac0; // ETH_A
eth1 = &gmac1; // ETH_B
eth2 = &gmac2; // ETH_C
};
...
};
U-boot usage[edit | edit source]
In U-Boot, only the ETH_A port is usable.
In the DESK-RZ-L-1.0.0 release, support for the i2c_0 bus is missing; as a result, the reset pins of the Ethernet PHYs cannot be driven by software.
As a workaround, the reset can be handled manually.
As shown in the image below, it is possible to control the reset of the ETH_A Ethernet PHY by pulling pin 6 of connector J54. This is done using a short wire with a 10–12 kΩ series resistor connected to pin 2 of the same J54 connector.
This operation should be performed only when the Ethernet interface is needed.
After using Ethernet in U-Boot, it is recommended to remove the wire before booting Linux.
Leaving it connected interferes with correct Linux operation, since Linux uses the GPIO expander exp_2 to control the PHY reset.
Example: kernel Image download via TFTP
Set IP addresses:
=> setenv ipaddr 192.168.0.168 => setenv serverip 192.168.0.169
If the PHY reset is not performed, the connection will fail:
=> ping 192.168.0.169 Could not get PHY for ethernet@80100000: addr 0 phy_connect() failed FAILED: 0 Using ethernet@80100000 device ARP Retry count exceeded; starting again ping failed; host 192.168.0.169 is not alive
Perform the manual reset.
Note that if the wire was already connected at power-on, it must be removed and reinserted, since the reset timing during boot is incorrect.
=> ping 192.168.0.169 ethernet@80100000 Waiting for PHY auto negotiation to complete...... done Using ethernet@80100000 device host 192.168.0.169 is alive =>
Test Image download:
=> run tftp_loadk
Using ethernet@80100000 device
TFTP from server 192.168.0.169; our IP address is 192.168.0.168
Filename 'boot/Image'.
Load address: 0xc4200000
Loading: #################################################################
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619.1 KiB/s
done
Bytes transferred = 20646400 (13b0a00 hex)
Linux messages at boot time[edit | edit source]
root@desk-t2h-usd-devel:~# dmesg | grep ethernet [ 2.352770] dwc-eth-dwmac 80100000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 2.362538] dwc-eth-dwmac 80100000.ethernet: PTP uses main clock [ 2.368605] dwc-eth-dwmac 80100000.ethernet: no reset control found [ 2.375386] dwc-eth-dwmac 92000000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 2.385154] dwc-eth-dwmac 92000000.ethernet: PTP uses main clock [ 2.391221] dwc-eth-dwmac 92000000.ethernet: no reset control found [ 2.397984] dwc-eth-dwmac 92010000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 2.407748] dwc-eth-dwmac 92010000.ethernet: PTP uses main clock [ 2.413814] dwc-eth-dwmac 92010000.ethernet: no reset control found [ 3.123590] dwc-eth-dwmac 80100000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 3.133331] dwc-eth-dwmac 80100000.ethernet: PTP uses main clock [ 3.143902] dwc-eth-dwmac 80100000.ethernet: no reset control found [ 3.157545] dwc-eth-dwmac 80100000.ethernet: GMAC use ETHSW timer 0 for PTP [ 3.169230] dwc-eth-dwmac 80100000.ethernet: User ID: 0x0, Synopsys ID: 0x52 [ 3.183513] dwc-eth-dwmac 80100000.ethernet: DWMAC4/5 [ 3.188683] dwc-eth-dwmac 80100000.ethernet: DMA HW capability register supported [ 3.196203] dwc-eth-dwmac 80100000.ethernet: RX Checksum Offload Engine supported [ 3.203721] dwc-eth-dwmac 80100000.ethernet: Wake-Up On Lan supported [ 3.210247] dwc-eth-dwmac 80100000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 3.218289] dwc-eth-dwmac 80100000.ethernet: device MAC address a2:2b:06:96:eb:7c [ 3.225807] dwc-eth-dwmac 80100000.ethernet: Enabled Flow TC (entries=8) [ 3.232541] dwc-eth-dwmac 80100000.ethernet: Using 32 bits DMA width [ 3.242723] dwc-eth-dwmac 92000000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 3.252469] dwc-eth-dwmac 92000000.ethernet: PTP uses main clock [ 3.258508] dwc-eth-dwmac 92000000.ethernet: no reset control found [ 3.265907] dwc-eth-dwmac 92000000.ethernet: GMAC use ETHSW timer 0 for PTP [ 3.273045] dwc-eth-dwmac 92000000.ethernet: User ID: 0x0, Synopsys ID: 0x52 [ 3.280131] dwc-eth-dwmac 92000000.ethernet: DWMAC4/5 [ 3.285297] dwc-eth-dwmac 92000000.ethernet: DMA HW capability register supported [ 3.292818] dwc-eth-dwmac 92000000.ethernet: RX Checksum Offload Engine supported [ 3.300336] dwc-eth-dwmac 92000000.ethernet: Wake-Up On Lan supported [ 3.306851] dwc-eth-dwmac 92000000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 3.314903] dwc-eth-dwmac 92000000.ethernet: device MAC address 5a:26:a8:eb:c5:2d [ 3.322422] dwc-eth-dwmac 92000000.ethernet: Enabled Flow TC (entries=8) [ 3.329156] dwc-eth-dwmac 92000000.ethernet: Using 32 bits DMA width [ 3.351900] dwc-eth-dwmac 92010000.ethernet: force_sf_dma_mode is ignored if force_thresh_dma_mode is set. [ 3.361652] dwc-eth-dwmac 92010000.ethernet: PTP uses main clock [ 3.367694] dwc-eth-dwmac 92010000.ethernet: no reset control found [ 3.375088] dwc-eth-dwmac 92010000.ethernet: GMAC use ETHSW timer 0 for PTP [ 3.382228] dwc-eth-dwmac 92010000.ethernet: User ID: 0x0, Synopsys ID: 0x52 [ 3.389320] dwc-eth-dwmac 92010000.ethernet: DWMAC4/5 [ 3.394494] dwc-eth-dwmac 92010000.ethernet: DMA HW capability register supported [ 3.402011] dwc-eth-dwmac 92010000.ethernet: RX Checksum Offload Engine supported [ 3.409529] dwc-eth-dwmac 92010000.ethernet: Wake-Up On Lan supported [ 3.416050] dwc-eth-dwmac 92010000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 3.424104] dwc-eth-dwmac 92010000.ethernet: device MAC address 52:10:cc:7b:cb:c4 [ 3.431624] dwc-eth-dwmac 92010000.ethernet: Enabled Flow TC (entries=8) [ 3.438358] dwc-eth-dwmac 92010000.ethernet: Using 32 bits DMA width [ 8.398894] dwc-eth-dwmac 92010000.ethernet eth2: PHY [stmmac-ethernet@80100000-0:02] driver [Microsemi VSC8541 SyncE] (irq=POLL) [ 8.403336] dwc-eth-dwmac 92010000.ethernet eth2: No Safety Features support found [ 8.403350] dwc-eth-dwmac 92010000.ethernet eth2: IEEE 1588-2008 Advanced Timestamp supported [ 8.406018] dwc-eth-dwmac 92010000.ethernet eth2: registered PTP clock [ 8.411212] dwc-eth-dwmac 92010000.ethernet eth2: configuring for phy/rgmii-id link mode [ 8.576478] dwc-eth-dwmac 92000000.ethernet eth1: PHY [stmmac-ethernet@80100000-0:01] driver [Microsemi VSC8541 SyncE] (irq=POLL) [ 8.579232] dwc-eth-dwmac 92000000.ethernet eth1: No Safety Features support found [ 8.579247] dwc-eth-dwmac 92000000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported [ 8.582118] dwc-eth-dwmac 92000000.ethernet eth1: registered PTP clock [ 8.593622] dwc-eth-dwmac 92000000.ethernet eth1: configuring for phy/rgmii-id link mode [ 8.782966] dwc-eth-dwmac 80100000.ethernet eth0: PHY [stmmac-ethernet@80100000-0:00] driver [Microsemi VSC8541 SyncE] (irq=POLL) [ 8.785710] dwc-eth-dwmac 80100000.ethernet eth0: No Safety Features support found [ 8.785726] dwc-eth-dwmac 80100000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported [ 8.786009] dwc-eth-dwmac 80100000.ethernet eth0: registered PTP clock [ 8.795468] dwc-eth-dwmac 80100000.ethernet eth0: configuring for phy/rgmii-id link mode
Check the interface with ifconfig[edit | edit source]
root@desk-mx93:~# ifconfig eth0
root@desk-t2h-usd-devel:~# ifconfig
...
eth0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 metric 1
ether a2:2b:06:96:eb:7c txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 86
eth1: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 metric 1
ether 6e:bf:f2:c5:e5:b6 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 89
eth2: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 metric 1
ether ca:bc:12:67:24:db txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 0 (0.0 B)
TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
device interrupt 92
...
Test with iperf3[edit | edit source]
root@desk-t2h-usd-devel:~# ifconfig eth0 192.168.0.168 up root@desk-t2h-usd-devel:~# iperf3 -c 192.168.0.111 Connecting to host 192.168.0.111, port 5201 [ 5] local 192.168.0.168 port 48270 connected to 192.168.0.111 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 97.5 MBytes 818 Mbits/sec 170 137 KBytes [ 5] 1.00-2.00 sec 100 MBytes 840 Mbits/sec 282 83.4 KBytes [ 5] 2.00-3.00 sec 100 MBytes 840 Mbits/sec 216 105 KBytes [ 5] 3.00-4.00 sec 100 MBytes 841 Mbits/sec 224 86.3 KBytes [ 5] 4.00-5.00 sec 100 MBytes 843 Mbits/sec 180 133 KBytes [ 5] 5.00-6.00 sec 97.4 MBytes 817 Mbits/sec 183 151 KBytes [ 5] 6.00-7.00 sec 101 MBytes 845 Mbits/sec 141 126 KBytes [ 5] 7.00-8.00 sec 98.9 MBytes 829 Mbits/sec 429 133 KBytes [ 5] 8.00-9.00 sec 97.5 MBytes 818 Mbits/sec 308 132 KBytes [ 5] 9.00-10.00 sec 99.8 MBytes 837 Mbits/sec 204 177 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 993 MBytes 833 Mbits/sec 2337 sender [ 5] 0.00-10.04 sec 991 MBytes 828 Mbits/sec receiver iperf Done. root@desk-t2h-usd-devel:~# ifconfig eth0 down root@desk-t2h-usd-devel:~# ifconfig eth1 192.168.0.168 up root@desk-t2h-usd-devel:~# iperf3 -c 192.168.0.111 Connecting to host 192.168.0.111, port 5201 [ 5] local 192.168.0.168 port 49240 connected to 192.168.0.111 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 102 MBytes 855 Mbits/sec 258 205 KBytes [ 5] 1.00-2.00 sec 100 MBytes 842 Mbits/sec 230 148 KBytes [ 5] 2.00-3.00 sec 98.9 MBytes 830 Mbits/sec 243 136 KBytes [ 5] 3.00-4.00 sec 101 MBytes 844 Mbits/sec 308 97.6 KBytes [ 5] 4.00-5.00 sec 100 MBytes 839 Mbits/sec 281 113 KBytes [ 5] 5.00-6.00 sec 100 MBytes 840 Mbits/sec 268 132 KBytes [ 5] 6.00-7.00 sec 99.4 MBytes 834 Mbits/sec 248 123 KBytes [ 5] 7.00-8.00 sec 99.4 MBytes 834 Mbits/sec 239 182 KBytes [ 5] 8.00-9.00 sec 100 MBytes 842 Mbits/sec 277 132 KBytes [ 5] 9.00-10.00 sec 101 MBytes 846 Mbits/sec 326 136 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1002 MBytes 841 Mbits/sec 2678 sender [ 5] 0.00-10.04 sec 1000 MBytes 835 Mbits/sec receiver iperf Done. root@desk-t2h-usd-devel:~# ifconfig eth1 down root@desk-t2h-usd-devel:~# ifconfig eth2 192.168.0.168 up root@desk-t2h-usd-devel:~# iperf3 -c 192.168.0.111 Connecting to host 192.168.0.111, port 5201 [ 5] local 192.168.0.168 port 48454 connected to 192.168.0.111 port 5201 [ ID] Interval Transfer Bitrate Retr Cwnd [ 5] 0.00-1.00 sec 102 MBytes 854 Mbits/sec 259 120 KBytes [ 5] 1.00-2.00 sec 100 MBytes 839 Mbits/sec 336 79.2 KBytes [ 5] 2.00-3.00 sec 99.7 MBytes 836 Mbits/sec 310 120 KBytes [ 5] 3.00-4.00 sec 99.6 MBytes 835 Mbits/sec 280 103 KBytes [ 5] 4.00-5.00 sec 99.3 MBytes 833 Mbits/sec 283 97.6 KBytes [ 5] 5.00-6.00 sec 99.8 MBytes 837 Mbits/sec 329 93.3 KBytes [ 5] 6.00-7.00 sec 100 MBytes 839 Mbits/sec 221 103 KBytes [ 5] 7.00-8.00 sec 100 MBytes 839 Mbits/sec 260 192 KBytes [ 5] 8.00-9.00 sec 99.6 MBytes 835 Mbits/sec 285 298 KBytes [ 5] 9.00-10.00 sec 100 MBytes 841 Mbits/sec 301 144 KBytes - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate Retr [ 5] 0.00-10.00 sec 1000 MBytes 839 Mbits/sec 2864 sender [ 5] 0.00-10.04 sec 998 MBytes 834 Mbits/sec receiver iperf Done. root@desk-t2h-usd-devel:~# dmesg ... [ 164.424817] dwc-eth-dwmac 80100000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx [ 164.424854] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready [ 224.838926] dwc-eth-dwmac 80100000.ethernet eth0: Link is Down [ 228.744827] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 228.745173] dwc-eth-dwmac 92000000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx [ 262.400967] dwc-eth-dwmac 92000000.ethernet eth1: Link is Down [ 275.688953] dwc-eth-dwmac 92010000.ethernet eth2: Link is Up - 1Gbps/Full - flow control rx/tx [ 275.689049] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready root@desk-t2h-usd-devel:~#
