DADA SOM/DADA Hardware/Peripherals/PRUSS

History
Issue Date	Notes
2025/09/01	First release

Peripheral PRUSS

The PRU Subsystem (PRUSS) - in the AM62x SoC - is a subset of the PRU Industrial Communication Subsystem (PRU-ICSS) found on other TI processors.

The programmable nature of the PRU cores provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the device.

The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate independently or in coordination with each other and can also work in coordination with the device-level host CPU.

Description

The Programmable Real-Time Unit Subsystem (PRUSS) consists of:

• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)
• Data RAMs per PRU core (DRAM)
• Instruction RAMs per PRU core (IRAM)
• Shared RAM (SRAM)
• Peripheral modules: UART0, ECAP0, IEP0, MDIO
• Interrupt Controller (INTC) per core

The PRUSS subsystem includes the following main features:

• Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1), each with:
  • 20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)
  • Asynchronous capture [Serial Capture Unit (SCU)] with 3-channel peripheral interface and Sigma-Delta demodulation support
• The 3-channel peripheral interface supports multiple different encoder protocols such as EnDAT 2.2, HDSL, and Tamagawa
  • program memory per PRU (PRU0_IRAM and PRU1_IRAM) with ECC
  • MAC (Multiplier with optional Accumulation)
  • CRC16/CRC32 hardware accelerator
  • RX XFR2VBUS
• Scratchpad Memory (SPAD) with 3 banks of 30 × 32-bit registers: 3 banks for the PRU0 and PRU1 cores
• 32 KB Shared general purpose memory RAM with ECC (Data RAM2), shared between PRU0 and PRU1
• Two 8 KB (shared) Data Memories with ECC (Data RAM0 and Data RAM1)
• 36-bit VBUSM Controller Port: optional address translation for all transactions to External Host
• 16 Software Events generated by 2 PRUs
• One Enhanced Capture Module (ECAP0)
• Interrupt Controller (INTC)
  • Up to 32 internal events, generated by modules, internal to the PRUSS
  • Up to 32 external events, generated by the system
  • Supports up to 10 interrupt channels
  • Generation of 8 Host interrupts:
    • 8 Host interrupts, exported from the PRUSS for signaling the Arm interrupt controllers (pulse and level provided)
  • Hardware prioritization of events
• Flexible power management support
• Integrated 32-bit Interconnect