DADA SOM/DADA Hardware/Peripherals/Industrial interfaces

History
Issue Date	Notes
2025/09/01	First release

Peripheral Industrial interfaces

The AM62x SoC in the DADA SOM has several industrial interfaces for automotive and industrial applications like Industrial HMI, driver monitoring systems, EV charging stations.

Description

The following industrial interfaces are available:

• 3x enhanced PWM modules (ePWM)
• 3x enhanced Quadrature Encoder Pulse modules (eQEP)
• 3x enhanced Capture modules (ECAP)
• Timer modules

Enhanced Pulse Width Modulation

The Enhanced Pulse Width Modulation (ePWM) interface (DSMIF) is able to generate complex pulse width waveforms with minimal CPU overhead or intervention.

The three ePWM modules support the following features:

• Dedicated 16-bit time-base counter with period and frequency control
• Two PWM outputs (EPWMxA and EPWMxB) that can be used as two independent PWM outputs with single-edge operation, two independent PWM outputs with dual-edge symmetric operation or one independent PWM output with dual-edge asymmetric operation
• Asynchronous override control of PWM signals through software
• Programmable phase-control support for lag or lead operation relative to other EPWM modules
• Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis
• Dead-band generation with independent rising and falling edge delay control
• Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault conditions
• A trip condition can force either high, low, or high-impedance state logic levels at PWM outputs
• Allows events to trigger both CPU interrupts and ADC start of conversions
• PWM chopping by a high-frequency carrier signal, useful for pulse transformer gate drives

Enhanced Quadrature Encoder Pulse modules

The Enhanced Quadrature Encoder Pulse (EQEP) peripheral is used for direct interface with a linear or rotary incremental encoder to get position, direction and speed information from a rotating machine for use in high performance motion and position control system.

The three eQEP include the following features:

• Input synchronization
• Three stage/six stage digital noise filter
• Quadrature decoder unit
• Position counter and control unit for position measurement
• Quadrature edge capture unit for low-speed measurement
• Unit time base for speed and frequency measurement
• Watchdog timer for detecting stalls
• EQEP inputs (A/B/INDEX and STROBE) are available at chip level
• EQEP phase error output is also available

Enhanced Capture modules

The Enhanced Capture (ECAP) module can be used for:

• Sample rate measurements of audio inputs
• Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor pulses
• Period and duty cycle measurements of pulse train signals
• Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors

The ECAP module includes the following features:

• 32-bit time base counter
• 4 × 32 bits event time-stamp capture registers (ECAP0_CAP1 through ECAP0_CAP4)
• 4-stage sequencer (Mod4 counter), synchronized to external events (ECAPx pin edges)
• Independent edge polarity (rising/falling edge) selection for all 4 sequenced time-stamp capture events
• Input capture signal pre-scaling (from 1 to 16)
• One-shot compare register (2 bits) to freeze captures after 1 to 4 time-stamp events
• Continuous mode capture of time-stamps in a four-deep circular buffer
• Absolute time-stamp capture
• Difference (Delta) mode time-stamp capture
• When not used in capture mode, the ECAP module can be configured as a single-channel PWM output

Timer modules

One Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation, is available with the following features:

GTC

• The GTC module provides a continuous running counter that can be used for time synchronization and debug trace time stamping and supports the following features:
  • 64-bit up counter (No rollover during the lifetime of the device)
  • Compatible with ARMv8 system counter requirements:
    • Disabled at power-up
    • Register definition and memory map aligned to ARMv8 definition
    • Implements memory-mapped counter control and status frames
  • Outputs reflected binary (Gray) encoded timer value for system timer bus distribution to other modules
  • Selectable counter bit output as a push event that can be used by CPTS modules, timers or interface protocols

Windowed Watchdog Timer (WWDT)

The Windowed Watchdog Timer (WWDT), implemented by using the Digital Windowed Watchdog (DWWD) function of the Real Time Interrupt (RTI) module in the device

The RTI modules include the following main features:

• Windowed Watchdog Timer (WWDT) feature
• Two independent 64 bit counter blocks (counter block0 or counter block1). Each block consists of one 32 bit up counter and one 32 bit free running counter
  • Two capture registers for capturing the prescale and free running counter on a special event.
• Free running counter 0 can be incremented by either the internal prescale counter or by an external event
• Four configurable compare registers for generating operating system ticks . Each event can be driven by either counter block0 or counter block1
• RTI clock input derived from any of the available clock sources, selectable in the System Module
• Optional capability to drive a pulse-width modulated signal out on an interrupt line

Real Time Clock

The RTC is to keep time of day and the important purpose is for Digital Rights management. Tamper proofing is needed to ensure that simply stopping, resetting, or corrupting the RTC does not go unnoticed so that if this occurs, the application can re-acquire the time of day from a trusted source.

The real-time clock (RTC) provides the following features:

• With Analog IP block: 2 digital voltage domains with integrated LVL/ISO cells, RTC or Always ON domain
• Without Analog IP block: 1 digital voltage domain, no lvl.iso
• 15 bit 32768Hz counter
• 48 bit seconds counter with +/- 1 30uS upto +/- 1 S drift adjustment every 4048 Seconds
• 256 bits of Scratch PAD
• 1 ON_OFF compare event, 48-bits / 1 OFF_ON compare event, 48-bits / 2 event outputs OFF_ON and ON_OFF to CORE
• Support active external 32768 Hz and inactive/gated 32768 Hz

• Some of the counter registers as general purpose

• Functional lockout, unlock by special vbusp sequence, DFT lockout, unlock by special 1500 sequence

• HOST PROCESSOR can issue OFF now cmd, update MMRs without polling, thanks to HW Shadow/Auto Sync, read time without polling, thanks to HW Shadow/Auto Sync

• External IOs (Optional): 4 wakeup inputs with active high/low including optional debounce
• Async wake up supported: 1 pmic_enable output