Additional UART on Linux (Naon)

Info Box Applies to Naon Applies to Maya Applies to Dido Applies to Linux

Introduction

In this article we will see how to enable an additional UART which can be used in a standard Linux application.

As an example, we use UART2.

Choose Pin Mux Option

UART2 TX/RX is available into different pins. We choose the following configuration:

Functional Pin	Naon Connector Phisical Pin	CPU Ball
UART2_TXD	J2.31	AD23
UART2_RXD	J2.30	AE23

Configure Pin Mux with Pin Mux Utility

Open the Pin Mux Utility and load the default Naon configuration provided with your development kit.

Into the Peripheral Interfaces box, right-click on UART2 device and choose View Pins

UART2 Interface View window opens and we can see the various UART2 options.

User can easily see that the pin we choose are already configured for GPMC peripheral. However, in our example design, we suppose that we don't need those lines.

Double click on Fcn6 column of AE23 and AD23 ball

As you can see, the Pin Mux Utility warn about a usage conflict. Double click on both lines in column Fcn5 to remove GPMC usage of those pins and the error disappears.

Now the Pin Mux Utility allow the user to export the generated source code. See TI wiki article for more details.

Rebuild U-Boot

Copy the generated source code (pinmux.h) and overwrite the original board/dave/naon/pinmux.h file inside the source tree.

The differences between the two files should look like the following patch

diff --git a/board/dave/naon/pinmux.h b/board/dave/naon/pinmux.h
index c1fccd6..0e6b2e2 100644
--- a/board/dave/naon/pinmux.h
+++ b/board/dave/naon/pinmux.h
@@ -208,8 +208,8 @@ MUX_VAL(PINCNTL168, (IEN | IPU | DISABLED )) /* safe_mode */\
 MUX_VAL(PINCNTL169, (IEN | IPD | DISABLED )) /* safe_mode */\
 MUX_VAL(PINCNTL170, (IEN | IPD | DISABLED )) /* safe_mode */\
 MUX_VAL(PINCNTL171, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL172, (IEN | IPD | DISABLED )) /* safe_mode */\
-MUX_VAL(PINCNTL173, (IEN | IPU | DISABLED )) /* safe_mode */\
+MUX_VAL(PINCNTL172, (IDIS | IPD | FCN6 )) /* UART2_RXD_MUX0 */\
+MUX_VAL(PINCNTL173, (IDIS | IPD | FCN6 )) /* UART2_TXD_MUX1 */\
 MUX_VAL(PINCNTL174, (IEN | IPD | DISABLED )) /* safe_mode */\
 MUX_VAL(PINCNTL175, (IEN | IPD | FCN1 )) /* VOUT[0]_FLD_MUX1 */\
 MUX_VAL(PINCNTL176, (IEN | IPD | FCN1 )) /* VOUT[0]_CLK */\

Configure Linux kernel

There's no need to change Linux source code or configuration, because UART devices are automatically registered at boot.

Here is an example of kernel boot messages on a Naon module.

[    0.940000] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    0.940000] omap_uart.0: ttyO0 at MMIO 0x48020000 (irq = 72) is a OMAP UART0
[    0.950000] console [ttyO0] enabled, bootconsole disabled
[    0.950000] console [ttyO0] enabled, bootconsole disabled
[    0.960000] omap_uart.1: ttyO1 at MMIO 0x48022000 (irq = 73) is a OMAP UART1
[    0.970000] omap_uart.2: ttyO2 at MMIO 0x48024000 (irq = 74) is a OMAP UART2
[    0.980000] omap_uart.3: ttyO3 at MMIO 0x481a6000 (irq = 44) is a OMAP UART3
[    0.990000] omap_uart.4: ttyO4 at MMIO 0x481a8000 (irq = 45) is a OMAP UART4
[    0.990000] omap_uart.5: ttyO5 at MMIO 0x481aa000 (irq = 46) is a OMAP UART5

Additional UART as Kernel Console

Configuring something different that the default (UART0) as kernel boot console requires a bit of more work, see also TI wiki for additional details.

First of all user should change, in U-Boot, the console command line argument, for example in console=ttyO2,115200n8

The file /etc/inittab into the target root file system should be updated too, to allow user login:

--- inittab.orig	2011-12-09 13:43:15.000000000 +0100
+++ inittab	2012-05-08 14:50:40.822591441 +0200
@@ -28,7 +28,7 @@ l5:5:wait:/etc/init.d/rc 5
 l6:6:wait:/etc/init.d/rc 6
 # Normally not reached, but fallthrough in case of emergency.
 z6:6:respawn:/sbin/sulogin
-S:2345:respawn:/sbin/getty 115200 ttyO0
+S:2345:respawn:/sbin/getty 115200 ttyO2
 # /sbin/getty invocations for the runlevels.
 #
 # The "id" field MUST be the same as the last

Even if it's rarely needed, if the user would like to enable earlyprintk on this UART, the following patch should be applied too:

diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 2ff424a..6adeae5 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -183,7 +183,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                DEBUG_LL_TI81XX(1, ti8148evm);
 
                 /* NAON uses UART1 */
-               DEBUG_LL_TI81XX(1, naon);
+                /* but we change this to support UART2 */
+               DEBUG_LL_TI81XX(3, naon);
 
        } while (0);
 }

Please note that, in this code, UART0 is referred as index 1. For this reason, for UART2, we use index 3.