Migrating from x86 architecture to Naon

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Introduction

Computational power achievable by system-on-chips built around Cortex-A8 processor make them an appealing solution for several applications that historically have been implemented on x86-based systems.

This article, written as a list of commonly asked questions, aims to help system integrators and developers who are used to work on x86-based machines to make a sort of comparison between these two different approaches in order to ease the migration process to Naon-based platforms.

Following images show simplified block diagram of x86-based PC-like architecture and Naon architecture.

x86-based PC-like architecture
Naon SOM architecture

This image shows in detail internal architecture of DM8148 digital media processor.

Naon SOM architecture

The first notable difference is about the integration level. By definition, system-on-chip such as DM8148, are designed to address embedded systems where footprint - in terms of PCB area and power budget - has to be minimized but, at same time, no significant compromise in performance is acceptable.

Reading of Deploying Embedded Linux Systems is recommended to complement issues here described.

Where is the BIOS?

Technically speaking, there is no BIOS. Typical configurations of true embedded systems implement a bootloader instead. This software is executed by processor right after it comes out of reset. Like BIOS, bootlader is responsible of:

  1. initializing the majority of hardware components - for example processor main PLLs and SDRAM controller
  2. loading operating system kernel; once this step is completed, bootloader or any part of it is not involved anymore until next bootstrap.

Bootlader usually implements a console - for example via UART port - that allows human operators to interact with the machine. This is extremely useful, for example, for maintenance operations and for development purposes.

What about GPU?

Modern PC graphics cards integrate a processor called GPU (Graphics processing unit) that accesses a dedicated SDRAM bank.

From the functional standpoint, on DM8148 graphics processing is performed by some blocks that are integrated in the chip. They are:

  1. High Definition Video Processing Subsystem (HDVPSS)
  2. High Definition Vieo Image Coprocessor (HDVICP2)
  3. SGX530 3D Graphics Engine
  4. Imaging Subsystem (ISS)
  5. Media controllers.

These blocks are tightly coupled with main general-purpose CPU (ARM Cortex-A8) and with SDRAM through a 128-bit wide 500 MHz internal bus called System Interconnect.

All of these entities share the system SDRAM. SDRAM is managed by sophisticated DMM/TILER module that optimizes its usage and implements priority management.