Bureaucrats, dave_user, Administrators
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{{Applies To Bora}}
{{Applies To BoraLite}}
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== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:Bora-reset-scheme.png | 700px900px]]
=== Reset signals ===
The available reset signals are described in detail in the following sections.
==== MRST (J2.116) ====
MRSTn is a de-bounced input for manual reset (for example to connect a push-button). This signal connected to the voltage monitor and is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== PORSTn (J2.114) ====This is a bidirectonal open-drain signal that is connected to Zynq's PS_SRST_B PS_POR_B and can be asserted by the following devices:
* a multi-rail voltage monitor that monitors 3.3VIN power rails and all of the rails generated by Bora's PSU. This monitor
** in case of a power glitch, asserts MEM_WPn signal in order to prevent any spurious write operation on flash memories too. MEM_WPn is 3.3V, push-pull, active low.
** has a timeout (set through an on-board capacitor) of about 1ms200 ms.
** provides MRSTn debounced input for manual reset (for example to connect a push-button). This signal is pulled-up to 3.3VIN through a 2.2kOhm resistor.
* a watchdog timer (Maxim MAX6373). For more details please refer to [[Watchdog_(Bora)|Watchdog]] section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
==== SYS_RSTn (J2.112) ====
This signal is connected to Zynq's PS_SRST_B and is pulled-up to 1.8V through a 20kOhm resistor.
==== PS_MIO51_501 (J2.106) ====
By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
==== PS_MIO50_501 (J2.104) ====
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
=== Pins connection ===
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Bora Pin'''
| style="background:#f0f0f0;" align="center" |'''Bora Lite Pin'''
|-
|MRST || J2.116 || J1.20
|-
|PORSTn || J2.114 || J1.20 (alternate mount option)
|-
|SYS_RSTn || J2.112 || J1.18
|-
|PS_MIO51_501 || J2.106 || J1.75
|-
|PS_MIO50_501 || J2.106 || -
|-
|}
=== Clock scheme ===
Bora is equipped with three independent active oscillators:
* processor (33.3 MHz)
* ethernet PHY (25 MHz)
* USB PHY (26 MHz)
Generally speaking, no clocks have to be provided by carrier board.
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