Changes

==== PS_MIO51_501 (J2.106Ethernet PHY reset) ====By default, this signal is connected to the on-board ETH Ethernet PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequenceregardless of the PL status.  For example, even if FPGA this is how the reset signal is not programmedhandled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. In case this signals must be used This initializes the component to implement different functions on carrier boardits default register values, alternative routing schemes which are available on request in order partly determined by the PHY's strapping pins.* Upon boot up, the Linux kernel issues a software reset via the BCMR register. If a hardware reset is required instead, the <code>macb</code> kernel driver and/or the related device tree properties have to free be modified for enabling this signal. For more details please refer to department salesfeature.