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→PS_MIO50_501 (J2.104)
By default, this signal is connected to on-board ETH PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
==== PS_MIO50_501 (J2.104USB PHY reset) ====By default, this signal is connected to the on-board USB PHY reset inputas depicted in the above figure. This scheme allows complete software control of the PHY hardware reset sequenceregardless of the PL status. For example, even if FPGA this is how the reset signal is handled in [https://wiki.dave.eu/index.php?title=BORA_SOM/BELK-L/General/Release_Notes&oldid=14810 BELK 4.1.5]: * U-Boot <code>board_init</code> routine generates a hardware reset pulse. This initializes the component to its default register values. * Linux kernel does not programmedissue any further hardware reset. In case this signals must be used to implement different functions on carrier boardIf a hardware reset is required upon Linux boot up, alternative routing schemes are available on request in order the <code>phy-ulpi</code> kernel driver and/or the according device tree properties have to free be modified for enabling this signal. For more details please refer to department salesfeature.
== Clock scheme ==
