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Reset scheme (BORAXpress)

1 byte added, 08:40, 4 March 2022
Clock scheme =
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
== Clock scheme ==
Bora is equipped with three independent active oscillators:
* processor (33.3 MHz)
4,650
edits

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