[[File:AxelUltra-reset-scheme.png | 800px]]
The available === PMIC_VSNVS ===Some signals that are related to reset signals circuitry are described pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in detail case of AxelUltra this pin is connected to 2V8-4V5 power rail* voltage applied to PMICS's LICELL pin** in the following sectionscase of AxelUltra this pin is connected to J1.126 pin (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''. For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' document.
=== CPU_PORn ===
Three different sources can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors several critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition ** MRSTn: this signal is connected to the RESET IN input of the voltage monitor. MRSTn is pulled-up to processor's I/O voltage with 2.2 kOhm resistor.
* watchdog timer: even if MX6 processor integrates a watchdog timer (WDT), an external WDT (Maxim MAX6373KA+) is avalible to maximize reliability
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state after reset occurrence.
=== Handling CPU initiated reset ===
'''By default, MX6 processor does not assert any external signal when it initiates a reset sequence'''. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal is driven by MX6's watchdog timer (WDT).
The two typical scenarios are:=== Handling CPU-initiated software reset ===# WDOG_RESET_B_DEB is '''By default, MX6 processor does not used (default): in this case assert any external signal when it initiates a CPU initiated software reset sequence . Also default software reset implementation does not guarantee that all processor registers are reset external devices such as SPI NOR flash memory. '''This may be criticalproperly'''. For example if boot memory these reasons, it is not reset properly, processor might be unable strongly recommended to boot correctly.# WDOG_RESET_B_DEB is used: in this case use a CPU initiated reset asserts WDOG_RESET_B_DEB signal different approach that, in turn, can be used to reset external devices. To implement this solution:#* software reset routines must configure WDT in order to assert WDOG_RESET_B_DEB signal#* WDOG_RESET_B_DEB must be configured properly at IOMUX controller level#* when asserted, WDOG_RESET_B_DEB must assert in turn either AxelUltra's PMIC_PWRON or AxelUltracombination with the use of a processor's CPU_PORn signal at carrier board level watchdog timer (see [[AxelEVB-Lite]] schematics as an exampleWDT). In case PMIC_PWRON is asserted, provides a complete power on cycle is perfomed and PMIC is full hardware reset too. In in case CPU_PORn is asserted instead, PMIC is not a software reset because its RESETBMCU pad is output onlyissued.
WDOG_RESET_B_DEB can be routed to SD1_DATA2 or SD1_DATA3 padsThis technique is implemented in [[Axel_Embedded_Linux_Kit_(XELK)|XELK]]. For more details please see descriptions ofIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 At software level, U-Boot and IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 registers in chapter ''IOMUX controller'' Linux kernel software reset routines make use of processor Reference Manual's WDT #2 to assert the WDOG2_B reset signal. About WDTThis signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to ''Watchdog Timer'' chapter insteadU22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.