Reset scheme (AxelLite)
Revision as of 13:35, 9 April 2014 by DevWikiAdmin (talk | contribs) (Created page with "{{InfoBoxTop}} {{AppliesToAxelLite}} {{InfoBoxBottom}} == Reset scheme and control signals == The following picture shows the simplified block diagram of reset scheme and vo...")
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Reset scheme and control signalsEdit
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
The available reset signals are described in detail in the following sections.
CPU_PORnEdit
The following devices can assert this active-low signal:
- PMIC
- multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.