Difference between revisions of "RIALTO SBC/Interfaces and Connectors/JTAG"

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[[Category:RIALTO SBC]]
 
[[Category:RIALTO SBC]]

Revision as of 14:09, 12 January 2024

History
Issue Date Notes
2023/01/09 First documentation release

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JTAG interface[edit | edit source]

Description[edit | edit source]

JTAG signals are routed to a dedicated connector on the RIALTO SBC PCB.

The connector is placed near the J60 mezzanine connector and J46 WiFi connector (please see the picture below).

JTAG connector

Signals[edit | edit source]

The following table describes the interface signals:

Pin# Pin name ARM-20 JTAG Notes
1 DGND Ground 4,6,8,10,12,14,16,18,20
2 JTAG_TCK 9
3 JTAG_TMS 7
4 JTAG_TDO 13
5 JTAG_TDI 5
6 JTAG_nTRST 3 keep the possibility to be unconnected
7 CPU_PORn 15 keep the possibility to be unconnected
8 JTAG_MOD Internally used as GPIO for USB OTG power enable in Host mode
9 n.c.
10 JTAG_VREF 1 3V3 internal pull-up