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The following paragraphs describe in detail the available PL I/O signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BORAXpressBora/BoraX)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
!XC7Z015
!XC7Z030
!Voltage PinsBank power supply pins
!I/O
!Differentials Pairs
* IO_L6P_T0_34 : CAN_RX
* IO_L19P_T3_34 : CAN_TX
== Routing Information ==
Routing implemented on Bora Xpress SoM allows the use of MGT serial tranceivers differential pairs ans FPGA's signals as differential pairs as well as single-ended.
[http://www.dave.eu/sites/default/files/files/BoraX-BoraXEVB-combined-routing.ods This spreadsheet] details routing rules applied to Bora Xpress's signals. Signals are grouped by bank number. The table details also the routing rules of the Bora Xpress SOM combined with Bora Xpress EVB highlighting routing to the FPGA Mezzanine Card (FMC) connector on Bora Xpress EVB.
