== Introduction ==
The following paragraphs describe in detail the available PL I/O pins signals and how they are routed to the BORA Xpress connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, BORA Xpress design allows carrier board to power two all three PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.For more details about PCB design considerations, please refer to the [[Integration_guide_(BORAXpressBora/BoraX)#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
|-
!FPGA Bank
!XC7Z015!XC7Z030!Bank power supply pins!I/O Voltage!Voltage PinsDifferentials Pairs|-|Bank 13|HR|HR!Notes|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99|50|24|-|Bank 34|HR|HP|J2.66<br>J2.68<br>J2.70<br>J2.72|50|24|-|Bank 35|HR|HP|J1.2<br>J1.66<br>J1.67<br>J1.68|50|24
|-
|}
FPGA I/O Bank definitions:
* '''HR''' = High Range I/O with support for I/O voltage from 1.2V to 3.3V
* '''HP''' = High Performance I/O with support for I/O voltage from 1.2V to 1.8V
Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:
* # indicates the bank number.
Highlighted rows are related to signals that are Here is a list of FPGA I/O actually used for particular functions into the inside BORA Xpress SOM. == FPGA Bank x ==:* IO_L6P_T0_34 : CAN_RXThe following table reports the available pins connected to bank x* IO_L19P_T3_34 :CAN_TX
{| class="wikitable" border="1"| alignRouting Information ="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conn. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-|}
== Routing implemented on Bora Xpress SoM allows the use of MGT serial tranceivers differential pairs ans FPGA Bank y ==The following table reports the available pins connected to bank y:'s signals as differential pairs as well as single-ended.
{| class="wikitable" border="1"| align="left" style="background[http:#f0f0f0;"|//www.dave.eu/sites/default/files/files/BoraX-BoraXEVB-combined-routing.ods This spreadsheet] details routing rules applied to Bora Xpress'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Conns signals. Signals are grouped by bank number. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-|} == FPGA Bank z == The following table reports details also the routing rules of the available pins connected Bora Xpress SOM combined with Bora Xpress EVB highlighting routing to bank z: {| class="wikitable" border="1"| align="left" style="background:#f0f0f0;"|'''Pin Name'''| align="left" style="background:#f0f0f0;"|'''Connthe FPGA Mezzanine Card (FMC) connector on Bora Xpress EVB. Pin'''| align="left" style="background:#f0f0f0;"|'''Notes'''|-|}
