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== Processor and memory subsystem ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Processor'''| align="center" style="background:#f0f0f0;" align="center"|'''Programmable logic cells'''| align="center" style="background:#f0f0f0;" align="center"|'''LUTs'''| align="center" style="background:#f0f0f0;" align="center"|'''Flip flops'''| align="center" style="background:#f0f0f0;" align="center"|'''Extensible block RAM'''| align="center" style="background:#f0f0f0;" align="center"|'''DSP slices'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak DSP performance'''
|-
| XC7Z010 ||28K Logic Cells ||17600 ||35200 ||240 KB ||80 ||58 GMACs
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||560 KB ||220 ||158 GMACs
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: XC7-Z0x0 comparison
|}
| '''Size min'''||8 MB
|-
| '''Size max'''||16 MB - This limitation is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed has not approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
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