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=== Integrated FPGA ===
The PL is derived from Xilinx’s 7 Series FPGA technology (Artix™-7 for the 7z010/7z020). The PL is used to extend the functionality to meet specific application requirements.
The PL provides many different types of resources including configurable logic blocks (CLBs), port and width configurable block RAM (BRAM), DSP slices with 25 x 18 multiplier, 48-bit accumulator and pre-adder (DSP48E1), a user configurable
analog to digital converter (XADC), clock management tiles (CMT), a configuration block with 256b AES for decryption and SHA for authentication, configurable I/Os (with differential signaling capabilities).
BORA customers are able to differentiate their product in hardware by customizing their applications using PL.
=== Power supply unit ===