dave_user, Administrators
5,188
edits
Changes
→NOR flash bank
{{InfoBoxBottom}}
<section begin="Body" />== Processor and memory subsystem = Design Overview =
The heart of Bora module is composed of the following components:
This chapter shortly describes the main Bora components.
=== Processor Info ===
The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Processor'''| align="center" style="background:#f0f0f0;" align="center"|'''Programmable logic cells'''| align="center" style="background:#f0f0f0;" align="center"|'''LUTs'''| align="center" style="background:#f0f0f0;" align="center"|'''Flip flops'''| align="center" style="background:#f0f0f0;" align="center"|'''Extensible block RAM'''| align="center" style="background:#f0f0f0;" align="center"|'''DSP slices'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak DSP performance'''
|-
| XC7Z010 ||28K Logic Cells ||17600 ||35200 ||240 KB ||80 ||58 GMACs
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||560 KB ||220 ||158 GMACs
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: XC7-Z0x0 comparison
|}
On PS side, the following peripherals and devices are connected to MIO signals:* Serial NOR fl ash (MIO [6:1])* NAND fl ash (MIO [0], [14:2])* UART1 (MIO [49:48])* I2C temperature sensor (MIO [47:46])* I2C MEMS RTC (MIO [47:46])* Gigabit Ethernet PHY (MIO [27:16])* USBOTG PHY (MIO [39:28])* SD/MMC (MIO [45:40]) Since these devices are considered essential, they have been connected to MIO signals in order to make them always functional, even if PL is not programmed. These peripherals represent the default configuration for the BORA SOM, but other configurations can be implemented changing the pin multiplexing === RAM memory bank ===
DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:
|}
=== NOR flash bank ===
NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:
| '''Size min'''||8 MB
|-
| '''Size max'''||16 MB - This limitation is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
|}
=== NAND flash bank ===
On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:
|}
== Power supply unit =Integrated FPGA ===The PL is derived from Xilinx’s 7 Series FPGA technology (Artix™-7 for the 7z010/7z020). The PL is used to extend the functionality to meet specific application requirements. The PL provides many different types of resources including configurable logic blocks (CLBs), port and width configurable block RAM (BRAM), DSP slices with 25 x 18 multiplier, 48-bit accumulator and pre-adder (DSP48E1), a user configurableanalog to digital converter (XADC), clock management tiles (CMT), a configuration block with 256b AES for decryption and SHA for authentication, configurable I/Os (with differential signaling capabilities). BORA customers are able to differentiate their product in hardware by customizing their applications using PL.
=== Power supply unit === Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to [[BORA_SOM/BORA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit]] page. === CPU module connectors ===
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
<section end="Body" />