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== Processor and memory subsystem ==
{| class="wikitable" |
| align="center" style="background:#f0f0f0;" align="center"|'''Processor'''| align="center" style="background:#f0f0f0;" align="center"|'''Programmable logic cells'''| align="center" style="background:#f0f0f0;" align="center"|'''LUTs'''| align="center" style="background:#f0f0f0;" align="center"|'''Flip flops'''| align="center" style="background:#f0f0f0;" align="center"|'''Total Block RAM'''| align="center" style="background:#f0f0f0;" align="center"|'''DSP slices'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak DSP performance (Symmetric FIR)'''| align="center" style="background:#f0f0f0;" align="center"|'''Serial Tranceivers'''| align="center" style="background:#f0f0f0;" align="center"|'''Peak Serial Transceiver performance'''
|-
| XC7Z015 ||74K Logic Cells ||46200 ||92400 ||3.3 Mb ||160 ||200 GMACs ||GTP (4 Lanes)||6.25 Gb/s
| XC7Z030 ||125K Logic Cells ||78600 ||157200 ||9.3 Mb ||400 ||593 GMACs||GTX (4 Lanes)||6.6 Gb/s
|-
|+ align="bottom" style="caption-side: bottom" align="bottom" | Table: XC7-Z0x0 comparison
|}
| '''Size min'''||8 MB
|-
| '''Size max'''||16 MB - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to BORA Xpress [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table | pinout specifications]].
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