| '''Size max'''||16 MB - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
|-
| '''Chip select'''||SPI_CS0n
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to BORA Xpress [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table | pinout specifications]].