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== PS interfaces ==
<section begin=PS/>
The 54 pins of the MIO module are assigned as reported in the following table:
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|}
<section end=PS/>
=== Gigabit Ethernet ===
<section begin=Ethernet/>
On-board Ethernet PHY (Micrel KSZ9031RNX) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the Gigabit Ethernet Controller (GEM) through RGMII interface on MIO bank 1, pins PS_MIO[16:27]. For further details (eg: connection and selection of the magnetics), please refer to the Micrel KSZ9031RNX datasheet. The following table describes the interface signals:
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|}
<section end=Ethernet/>
=== USB ===
<section begin=USB/>
BORA Lite provides one USB 2.0 (Full Speed, up to 480 Mbps) port with on-board PHY (SMSC USB3317) and support to the On-The-Go (OTG) specifications. The transceiver is connected to the USB1 controller (MIO bank 1, pins PS_MIO[28:39]). The following table describes the interface signals:
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|}
<section end=USB/>
=== Quad-SPI ===
<section begin=SPI/>
Quad-SPI is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. The following table describes the interface signals:
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|}
<section end=SPI/>
=== Static memory controller ===
<section begin=NAND/>
Static memory controller (SMC) signals are routed to the connectors to connect an external flash NAND memory chip. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|NAND_CS0 || J1.122 || NAND flash chip select || MIO bank 0, pin 0
|-
|NAND_IO0 || J1.119 || NAND I/O 0 || MIO bank 0, pin 5
|-
|NAND_IO1 || J1.129 || NAND I/O 1 || MIO bank 0, pin 6
|-
|NAND_IO2 || J1.121 || NAND I/O 2 || MIO bank 0, pin 4
|-
|NAND_IO3 || J1.124 || NAND I/O 3 || MIO bank 0, pin 13
|-
|NAND_IO4 || J1.126 || NAND I/O 4 || MIO bank 0, pin 9
|-
|NAND_IO5 || J1.128 || NAND I/O 5 || MIO bank 0, pin 10
|-
|NAND_IO6 || J1.132 || NAND I/O 6 || MIO bank 0, pin 11
|-
|NAND_IO7 || J1.134 || NAND I/O 7 || MIO bank 0, pin 12
|-
|NAND_WE || J1.123 || NAND write enable || MIO bank 0, pin 3
|-
|NAND_ALE || J1.125 || NAND address latch || MIO bank 0, pin 2
|-
|NAND_RB || J1.136 || NAND ready/busy || MIO bank 0, pin 8
|-
|NAND_CLE || J1.138 || NAND command latch enable || MIO bank 0, pin 7
|-
|}
<section end=NAND/>
=== I²C0 ===
<section begin=I2C0/>
This I²C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range up to 400 Kb/s. I²C0 is internally connected to the following devices:
* [[EEPROM (BoraLite)|EEPROM]]: Microchip 24AA32AT(Address: 0xA0)
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|}
<section end=I2C0/>
=== SD/SDIO ===
<section begin=SDIO/>
The SD/SDIO controller controller is compatible with the standard SD Host Controller Specification Version 2.0
Part A2. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards. The SD/SDIO controller also supports MMC3.31.
|-
|}
<section end=SDIO/>
=== UART1 ===
<section begin=UART1/>
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. UART1 port is routed to the SOM connectors as a 2-wire interface. The following table describes the interface signals:
|-
|}
<section end=UART1/>
=== JTAG ===
<section begin=JTAG/>
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. This JTAG port grants access to the device chain composed of both the CPU core and the FPGA part. The following table describes the interface signals:
More information about the JTAG connector at the [[On_board_JTAG_connector_(BoraLite)|this page]]
<section end=JTAG/>
