a000298_approval, dave_user
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FPGA bitstream - that in turn is built upon [http://opencores.org/project,highload this core] - allocates most of FPGA resources. All of them are clocked by one clock signal whose frequency is selectable by the PS at runtime. This allows to flexibly change DUT current absorption and, consequently, the heat it generates.
==Configuration #1==
===Testbed===
Measurements have been performed on the following platform:
* BoraLite SOM: DBTD4111I0R
**this model is based on Zynq XC7Z020-1I (Tj: '''-40°C / +100°C''')
* carrier board: [[BoraXEVB]]
* processor frequency: '''667 MHz'''
* FPGA frequency
**1 MHz (Tamb = +85°C)
**140 MHz (Tamb = +-40°C)
*U-Boot: <code>2017.01-belk-4.1.1 (Jan 08 2020 - 16:52:16) [belk-4.1.1]</code>
*Linux kernel: <code>4.9.0-belk-4.1.0-xilinx #1 SMP PREEMPT Tue Dec 24 11:34:28 CET 2019 armv7l armv7l armv7l GNU/Linux</code>
*root file system mounted over Gigabit Ethernet link.
Please note that, when Tamb has been set to +85°C, the Bora SOM has been coupled to a passive heat sink to prevent exceeding maximum Zynq's junction temperature.
At the application level, PS executes concurrently several tasks including:
*two instances of [https://github.com/Explorer09/cpustress-sources/blob/master/cpuburn/cpuburn-1.4a/ARM/burnCortexA9.s <code>burnCortexA9</code>]
*endless loop of many MTD tests on NAND device
*periodic reading of Zynq's ADCs
*periodic reading of voltage/current probe (Texas Instruments INA226) connected to the SOM's power rail
*one instance of [http://pyropus.ca/software/memtester/ <code>memtester</code>], exercising 50 MByte of SDRAM
*endless loop of writing/reading/verifying operations on microSD card
*endless loop of iperf test through ethernet
*endless loop of writing/reading/verifying operations on memory stick connected to the USB port.
===Results===
*Tamb: temperature of the ambient surrounding the DUT
*Tj_max: maximum Zynq's junction temperature measured during the test
*P_max: maximum power absorption of Bora SOM
{| class="wikitable" border="1"
!Tamb [°C]
!Tj_max [°C]
!FPGA clock frequency [MHz]
!P_max [W]
|-
|85
|116.4 [1]
|1
|7.9
|-
| -40
|81.9
|140
|7.2
|-
|}
[1] In spite of the use of heat sink, this value exceeds maximum valued declared by the manufacturer. This is acceptable in case of stress tests, where it is possible that parts of the DUT get damaged.