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Power (BORAXpress)

1,365 bytes added, 14:29, 3 November 2015
→‎Power Supply Unit (PSU) and recommended power-up sequence
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==Introduction==
This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.
Each row in the pinout tables contains the following information:
* Pin: reference to the connector pin* Pin Name: pin == Power Supply Unit (signalPSU) name on the BORA Xpress connectorsand recommended power-up sequence ==* Internal connections: connections to the BORA Xpress components** CPU.<x> : pin connected to CPU (processing Implementing correct power-up sequence for Zynq-based system) pad named <x>** FPGAis not a trivial task because several power rails are involved.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to Bora Xpress SOM simplifies this task and embeds all the CAN transceiver** LANneeded circuitry.<x> : pin connected to the LAN PHY** USBThe following picture shows a simplified block diagram of power supply subsystem.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* Ball/pin #: Component ball/pin number connected to signal* Supply Group: Power Supply Group* Type: pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: I/O voltage levels
==J1 odd pins (1 to 139)==[[File:Borax-power-sequence.png|thumb|center|600px|BoraX PSU simplified block diagram]]
==J1 even pins (2 to 140)==
==J2 odd pins The recommended power-up sequence is:# main power supply rail (3.3VIN) ramps up# carrier board circuitry raises CB_PWR_GOOD; this indicates 3.3VIN rail is stable (1 )# Bora Xpress's PSU enables and sequences DC/DC regulators to turn circuitry on# SOM_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). Please note that '''FPGA Bank 13, FPGA Bank 34 and FPGA Bank 35 of the PL must be powered by carrier board even if they are not used to 139implement any function'''. Three dedicated power rails are available for this purpose (VDDIO_BANK34, VDDIO_BANK35 and VDDIO_BANK13)==, '''offering the system designer the freedom to select the I/O voltage of these three banks'''. The power rails of these banks are enabled by the SOM_PGOOD signal and are connected to the I/O power supply rail provided by the carrier board.
==J2 even pins (2 Bora Xpress's PSU is designed to 140)==be robust against misbehaving power rails. However, the recommended power-on ramp for core and I/O supplies ranges from 1 to 6 V/ms.
==J3 odd pins (1 to 139)=='''N.B.''': Regarding power off, it is recommended that I/O supply is turned off before core supply.
(1) This step is not mandatory and CB_PWR_GOOD can be left floating. CB_PWR_GOOD is provided to prevent, if necessary, Bora Xpress's PSU to turn on during ramp of carrier board 3.3VIN rail. Depending on carrier board's PSU design, this may lead to undesired glitches during ramp-up. ==J3 even pins (2 XCN15034 and power-off sequence ==On 29th September 2015 Xilinx released a Product Change Notice indicating new power on/off requirements about Zynq components.A specific analysis has been undertaken with the help of Xilinx technical support to verify the compliance of Bora Xpress with respect to the new requirements. This activity has led to the following recommendation: in order to prevent situations that might not fulfill such requirements, 3.3VIN off ramp speed must not exceed 47V/s. For more details about this matter, please refer to 140)AR #65240<ref name="AR65240">http://www.xilinx.com/support/answers/65240.html</ref> and XCN15034<ref name="XCN15034">http://www.xilinx.com/support/documentation/customer_notices/xcn15034.pdf</ref>.
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