Pinout (Naon)

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Naon am387x-dm814x.png Applies to Naon

This chapter contains the pinout description of the Naon module, grouped in four tables (two – odd and even pins – for each connector) that report the pin mapping of the two 140 pin Naon connectors. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Naon connectors
  • Internal connections: connections to the Naon components
    • CPU.<x> : pin connected to CPU pad named <x>
    • KEY.<x>: pin connected to the keypad controller
    • TSC.<x> : pin connected to the touchscreen controller
    • EEPROM.<x> : pin connected to the EEPROM
    • CAN.<x> : pin connected to the CAN transceiver
    • PMIC.<x> : pin connected to the Power Manager IC
    • LAN.<x> : pin connected to the LAN PHY
    • USB.<x> : pin connected to the USB transceiver
    • SV.<x>: pin connected to voltage supervisor
    • MTR: pin connected to voltage monitors
  • Ball/pin #: Component ball/pin number connected to signal
  • Supply Group: Power Supply Group
  • Type: pin type
    • I = Input
    • O = Output
    • Z = High impedance
    • S = Power supply voltage
    • G = Ground
    • A = Analog signal
    • Voltage: I/O voltage levels

J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.1 DGND DGND - G
J1.3 DGND DGND - G
J1.5 USB0_DM CPU.USB0_DM AH11 A, I/O
J1.7 UART0_RXD CPU.UART0_RXD AH5 I
J1.9 VBAT PMIC.VBACKUP D7 S
J1.11 MDIO_MDCLK CPU.MDCLK/GP1[11] H28 I/O (1)
J1.11 UART4_RXD/GP3_1 CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UART4_RXD/GP3[1] AG25 I/O (1)
J1.13 ADC_GND DGND - G
J1.15 ADC0_IN TSC.IN1 16 A
J1.17 USB0_ID CPU.USB0_ID AG10 A I
J1.19 UART0_RTSn/DCAN1_RX CPU.UART0_RTSn/UART4_TXD/DCAN1_RX/SPI[1]_SCS[2]n/SD2_SDCD AF5 I/O
J1.21 UART0_CTSn/DCAN1_TX CPU.UART0_RTSn/UART4_RXD/DCAN1_TX/SPI[1]_SCS[3]n/SD0_SDCD AE6 I/O
J1.23 VIN0A_D16/CAM_D8 CPU.VIN[0]A_D[16]/CAM_D[8]/I2C[2]_SCL/GP0[10] AA21 I/O
J1.25 VIN0A_D17/CAM_D9 CPU.VIN[0]A_D[17]/CAM_D[9]/EMAC[1]_RMRXER/GP0[11] AB21 I/O
J1.27 VIN0A_D18/CAM_D10 CPU.VIN[0]A_D[18]/CAM_D[10]/EMAC[1]_RMRXD[1]/I2C3[3]_SCL/GP0[12] AF20 I/O
J1.29 VIN0A_D19/CAM_D11 CPU.VIN[0]A_D[19]/CAM_D[11]/EMAC[1]_RMRXD[0]/I2C3[3]_SDA/GP0[13] AF21 I/O
J1.31 VIN0A_D20/CAM_D12 CPU.VIN[0]A_D[20]/CAM_D[12]/EMAC[1]_RMCRSDV/SPI[3]_SCS[0]n/GP0[14] AC17 I/O
J1.33 VIN0A_D21/CAM_D13 CPU.VIN[0]A_D[21]/CAM_D[13]/EMAC[1]_RMTXD[0]/SPI[3]_SCLK/GP0[15] AE18 I/O
J1.35 DGND DGND - G
J1.37 SPI1_D0/GP1_26 CPU.SPI[1]_D[0]/GP1[26] AA6 I/O
J1.39 TSC_XP TSC.X+ 2 I Please consider the use of ESD protection devices on carrier board when these pins are connected to actual touch screen.
J1.41 TSC_XM TSC.X- 4 I
J1.43 TSC_YP TSC.Y+ 3 I
J1.45 TSC_YM TSC.Y- 5 I
J1.47 VOUT0_R_CR9 CPU.VOUT[0]_R_CR[9] AC13 O
J1.49 VOUT0_R_CR7 CPU.VOUT[0]_R_CR[7] AF12 O
J1.51 VOUT0_R_CR5 CPU.VOUT[0]_R_CR[5] AF8 O
J1.53 VOUT0_G_Y_YC9 CPU.VOUT[0]_G_Y_YC[9] AF14 O
J1.55 VOUT0_G_Y_YC7 CPU.VOUT[0]_G_Y_YC[7] AD14 O
J1.57 VOUT0_G_Y_YC5 CPU.VOUT[0]_G_Y_YC[5] AB12 O
J1.59 VOUT0_B_CB_C9 CPU.VOUT[0]_B_CB_C[9] AG15 O
J1.61 VOUT0_B_CB_C7 CPU.VOUT[0]_B_CB_C[7] AB10 O
J1.63 DGND DGND - G
J1.65 VOUT0_B_CB_C5 CPU.VOUT[0]_B_CB_C[5] AD15 O
J1.67 TIM2_IO/GP0_8 CPU.AUD_CLKIN1/MCA[0]_AXR[8]/MCA[1]_AHCLKX/MCA[4]_AHCLKX/ATL_CLKOUT2/EDMA_EVT3/TIM2_IO/GP0[8] R5 I/O
J1.69 VOUT0_VSYNC CPU.VOUT[0]_VSYNC AB13 O
J1.71 VOUT0_CLK CPU.VOUT[0]_CLK AD12 O
J1.73 KP_ROW1 KEY.ROW1 24 I
J1.75 KP_ROW3 KEY.ROW3 2 I
J1.77 EMAC1_RGMII_TXD2 CPU.EMAC[0]_MTXD[4]/EMAC[1]_RMRXER/GPMC_A[11]/UART4_RTSn G23 I/O (1)
J1.77 KP_ROW7 KEY.ROW7 8 I (1)
J1.79 EMAC1_RGMII_TXD1 CPU.EMAC[0]_MTXD[1]/GPMC_A[8]/UART4_RXD H25 I/O (1)
J1.79 KP_COL4 KEY.COL4 4 I (1)
J1.81 KP_COL1 KEY.COL1 12 I
J1.83 KP_COL3 KEY.COL3 3 I
J1.85 EMAC1_RGMII_TXD0 CPU.EMAC[0]_MTXD[3]/EMAC[1]_RMRXD[1]/GPMC_A[10]/UART4_CTSn H23 I/O (1)
J1.85 KP_COL6 KEY.COL6 9 I
J1.87 EMAC1_RGMII_TXC CPU.EMAC[0]_MTXD[5]/EMAC[1]_RMCRSDV/GPMC_A[12]/UART1_RXD F27 I/O (1)
J1.87 SPI1_SCS0N/GP1_16 CPU.SPI[1]_SCS[0]n/GP1[16] AD3 I/O
J1.89 DGND DGND G
J1.91 EMAC_REFCLK CPU.EMAC_RMREFCLK/TIM2_IO/GP1[10] J27 I/O
J1.93 USB0_DRVVBUS CPU.USB0_DRVVBUS/GP0[7] AF11 I/O
J1.95 USB1.VBUS CPU.USB1_VBUSIN AG14 A, I
J1.97 HDMI_DP2 CPU.HDMI_DP2 AG21 O
J1.99 HDMI_DN2 CPU.HDMI_DN2 AH21 O
J1.101 HDMI_DP1 CPU.HDMI_DP1 AG20 O
J1.103 HDMI_DN1 CPU.HDMI_DN1 AH20 O
J1.105 HDMI_DP0 CPU.HDMI_DP0 AG19 O
J1.107 HDMI_DN0 CPU.HDMI_DN0 AH19 O
J1.109 HDMI_CLKP CPU.HDMI_CLKP AG18 O
J1.111 HDMI_CLKN CPU.HDMI_CLKN AH18 O
J1.113 DGND DGND G
J1.115 TIM5_IO/GP0_19 CPU.MCA[3]_AXR[1]/TSI[0]_PACVAL/TIM5_IO/GP0[19] G2 I/O
J1.117 VIN1A_HSYNC/GP2_28 CPU.VOUT[1]_CLK/EMAC[1]_MTCLK/VIN[1]A_HSYNC/PATA_HDDIR/GP2[28] AE24 I/O
J1.119 SD1_DAT0 CPU.SD1_DAT[0] P1 I/O
J1.121 SD1_DAT1 CPU.SD1_DAT[1]_SDIRQn P5 I/O
J1.123 SD1_DAT2 CPU.SD1_DAT[2]_SDRWn P4 I/O
J1.125 SD1_DAT3 CPU.SD1_DAT[3] P6 I/O
J1.127 SD1_DAT4 CPU.SD0_DAT[0]/SD1_DAT[4]/SC1_DATA/GP0[3] R7 I/O
J1.129 SD1_DAT5 CPU.SD0_DAT[1]_SDIRQn/SD1_DAT[5]/SC1_CLK/GP0[4] Y5 I/O
J1.131 TV_OUT1 CPU.TV_OUT0 AH24 O
J1.133 TV_OUT2 CPU.TV_OUT1 AH22 O
J1.135 SD1_CMD CPU.SD1_CMD/GP0[0] P2 I/O
J1.137 SD1_CLK CPU.SD1_CLK P3 O
J1.139 DGND DGND - G

J1 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.2 DGND DGND - G
J1.4 DGND DGND - G
J1.6 USB0_DP CPU.USB0_DP AG11 A, I/O
J1.8 UART0_TXD CPU.UART0_TXD AG5 O
J1.10 EEPROM_A0 EEPROM.A1 A1 O
J1.12 EEPROM_A1 EEPROM.A2 A2 I/O
J1.14 MDIO_MDIO CPU.MDIO/GP1[12] P24 I/O (1)
UART4_TXD_GP3_2 CPU.VOUT[1]_B_CB_C[5]/EMAC[1]_MRXD[1]/VIN[1]A_D[2]/UART4_TXD/GP3[2] AF25 I/O (1)
J1.16 USB0_VBUS CPU.USB0_VBUSIN AG12 A, I
J1.18 VIN0A_D13_BD5/CAM_RESET CPU.VIN[0]A_D[13]_BD[5]/CAM_RESET/GP2[18] AF17 I/O
J1.20 VIN0A_D14_BD6/CAM_STROBE CPU.VIN[0]A_D[14]_BD[6]/CAM_STROBE/GP2[19] AC12 I/O
J1.22 VIN0A_D11_BD3/CAM_WEn CPU.VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[16] AH17 I/O
J1.24 VIN0A_D15_BD7/CAM_SHUTTER CPU.VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/GP2[20] AC14 I/O
J1.26 VIN0A_CLK/GP2_2 CPU.VIN[0]A_CLK/GP2[2] AB20 I/O
J1.28 DGND DGND - G
J1.30 VIN0A_D0/GP1_11 CPU.VIN[0]A_D[0]/GP1[11] AF9 I/O
J1.32 VIN0A_D1/GP1_12 CPU.VIN[0]A_D[1]/GP1[12] AB11 I/O
J1.34 SPI1_SCLK/GP1_17 CPU.SPI[1]_SCLK/GP1[17] AC3 I/O
J1.36 VIN0A_D2/GP2_7 CPU.VIN[0]A_D[2]/GP2[7] AC9 I/O
J1.38 CAM_D4 CPU.VIN[0]B_FLD/CAM_D[4]/PATA_DIOWn/GP0[21] AD17 I/O
J1.40 VIN0A_FLD/CAM_D5 CPU.VIN[0]A_FLD/CAM_D[5]/PATA_CS[0]n/GP0[20] AC22 I/O
J1.42 CAM_D6 CPU.VIN[0]B_DE/CAM_D[6]/GP0[19] AC15 I/O
J1.44 VIN0A_DE/CAM_D7 CPU.VIN[0]A_DE/CAM_D[7]/GP0[18] AB17 I/O
J1.46 VOUT0_R_CR8 CPU.VOUT[0]_R_CR[8] AE8 O
J1.48 VOUT0_R_CR6 CPU.VOUT[0]_R_CR[6] AF6 O
J1.50 VOUT0_R_CR4 CPU.VOUT[0]_R_CR[4] AA9 O
J1.52 DGND DGND - G
J1.54 VOUT0_G_Y_YC8 CPU.VOUT[0]_G_Y_YC[8] AE14 O
J1.56 VOUT0_G_Y_YC6 CPU.VOUT[0]_G_Y_YC[6] AA8 O
J1.58 VOUT0_G_Y_YC4 CPU.VOUT[0]_G_Y_YC[4] AB8 O
J1.60 VOUT0_B_CB_C8 CPU.VOUT[0]_B_CB_C[8] AF15 O
J1.62 VOUT0_B_CB_C6 CPU.VOUT[0]_B_CB_C[6] AC10 O
J1.64 VOUT0_B_CB_C4 CPU.VOUT[0]_B_CB_C[4] AD11 O
J1.66 VOUT0_AVID/VOUT0_FLD/GP2_21 CPU.VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_SCLK/TIM7_IO/GP2[21] AA10 O
J1.68 VOUT0_HSYNC CPU.VOUT[0]_HSYNC AC11 O
J1.70 TIM4_IO/GP0_18 CPU.MCA[3]_AXR[0]/TSI[0]_DATA/TIM4_IO/GP0[18] G1 I/O
J1.72 KP_ROW0 KEY.ROW0 23 I
J1.74 KP_ROW2 KEY.ROW2 1 I
J1.76 DGND DGND - G
J1.78 EMAC1_RGMII_RXC CPU.EMAC[0]_GMTCLK/GPMC_A[6]/SPI[2]_D[1] K23 I/O (1)
J1.78 KP_ROW5 KEY.ROW5 6 I (1)
J1.80 EMAC1_RGMII_RXD3 CPU.EMAC[0]_MTXD[0]/GPMC_A[7]/SPI[2]_D[0] J24 I/O (1)
J1.80 KP_ROW4 KEY.ROW4 5 I (1)
J1.82 KP_COL0 KEY.COL0 13 I
J1.84 KP_COL2 KEY.COL2 11 I
J1.86 EMAC1_RGMII_RXD2 CPU.EMAC[0]_MTXEN/EMAC[1]_RMTXEN/GPMC_A[15]/UART1_RTSn J23 I/O (1)
J1.86 KP_ROW6 KEY.ROW6 7 I (1)
J1.88 EMAC1_RGMII_RXD1 CPU.EMAC[0]_MRXDV/GPMC_A[5]/SPI[2]_SCLK K22 I/O (1)
J1.88 KP_COL5 KEY.COL5 10 I (1)
J1.90 SPI1_D1/GP1_18 CPU.SPI[1]_D[1]/GP1[18] AA3 I/O
J1.92 VIN0A_D22/CAM_D14 CPU.VIN[0]A_D[22]/CAM_D[14]/EMAC[1]_RMTXD[1]/SPI[3]_D[1]/GP0[16] AC21 I/O
J1.94 VIN0A_D23/CAM_D15 CPU.VIN[0]A_D[23]/CAM_D[15]/EMAC[1]_RMTXEN/SPI[3]_D[0]/GP0[17] AC16 I/O
J1.96 CAN_H CPU.DCAN0_TX/UART2_TXD/I2C[3]_SDA/GP1[0] AH6 I/O
J1.98 CAN_L CPU.DCAN0_RX/UART2_RXD/I2C[3]_SCL/GP1[1] AG6 I/O
J1.100 DGND DGND - G
J1.102 SD1_DAT6 CPU.SD0_DAT[2]_SDRWn/SD1_DAT[6]/SC1_RST/GP0[5] Y3 I/O
J1.104 SD1_DAT7 CPU.SD0_DAT[3]/SD1_DAT[7]/SC1_VCCEN/GP0[6] Y4 I/O
J1.106 EMAC1_RGMII_RXD0 CPU.EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[0]/GPMC_A[13]/UART1_TXD J22 I/O (1)
J1.106 KP_COL7 KEY.COL7 22 I (1)
J1.108 EMAC1_RGMII_RXCTL CPU.EMAC[0]_MRXD[3]/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/UART5_RXD J25 I/O
J1.110 EMAC1_RGMII_TXCTL CPU.EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[0]/GPMC_A[9]/UART4_TXD H22 I/O
J1.112 EMAC1_RGMII_TXD3 CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn H24 I/O
J1.112 TCLKIN/GP0_30 CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn T2 I/O
J1.114 TIM6_IO/GP0_24 CPU.MCA[4]_AXR[1]/TSI[2]_PACVAL/TIM6_IO/GP0[24] J4 I/O
J1.116 VIN0A_D3/GP2_8 CPU.VIN[0]A_D[3]/GP2[8] AE12 I/O
J1.118 USB1_DRVVBUS CPU.AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_AHCLKX/MCA[3]_AHCLKX/ATL_CLKOUT1/ATL_CLKOUT0/VCX_VIC[0]/USB1_DRVVBUS L5 I/O
J1.120 VIN0A_D4/GP2_9 CPU.VIN[0]A_D[4]/GP2[9] AH8 I/O
J1.122 VIN0A_D5/GP2_10 CPU.VIN[0]A_D[5]/GP2[10] AG16 I/O
J1.124 SD0_CLK CPU.SD0_CLK/GP0[1] Y6 I/O
J1.126 DGND DGND - G
J1.128 SD2_SCLK CPU.SD2_SCLK/GP1[15] M23 I/O
J1.130 SD0_CMD CPU.SD0_CMD/SD1_CMD/GP0[2] N1 I/O
J1.132 VIN1A_D0/GP3_0 CPU.VOUT[1]_B_CB_C[3]/EMAC[1]_MRCLK/VIN[1]A_D[0]/UART4_CTSN/GP3[0] AH25 I/O
J1.134 VIN1A_CLK/GP2_31 CPU.VOUT[1]_AVID/EMAC[1]_MRXER/VIN[1]A_CLK/UART4_RTSn/TIM6_IO/GP2[31] Y22 I/O
J1.136 HDMI_I2C_SCL CPU.I2C[1]_SCL/HDMI_SCL AF24 I/O
J1.138 HDMI_I2C_SDA CPU.I2C[1]_SDA/HDMI_SDA AG24 I/O
J1.140 DGND DGND - G

J2 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J2.1 3.3V +3V3 - S
J2.3 DGND DGND - G
J2.5 GPMC_D0 CPU.GPMC_D[0]/BTMODE[0] U26 I/O
J2.7 GPMC_D2 CPU.GPMC_D[2]/BTMODE[2] V27 I/O
J2.9 GPMC_D4 CPU.GPMC_D[4]/BTMODE[4] V26 I/O
J2.11 GPMC_D6 CPU.GPMC_D[6]/BTMODE[6] U25 I/O
J2.13 CPU_NMIn CPU.NMIn H7 I
J2.15 CPU_RESETn CPU.RESETn J5 I
J2.17 VOUT1_G_Y_YC4/GP3_8 CPU.VOUT[1]_G_Y_YC[4]/EMAC[1]_MRXD[7]/VIN[1]A_D[9]/PATA_D[1]/GP3[8] W22 I/O
J2.19 SPI0_SCS1n/SD1_SDCD/SATA_ACT0_LED CPU.SPI[0]_SCS[1]n/SD1_SDCD/SATA_ACT0_LED/EDMA_EVT1/TIM4_IO/GP1[6] AE5 I/O
J2.21 GPMC_A0 CPU.VOUT1_B_CB_C[2]/GPMC_A[0]/VIN[1]A_D[7]/HDMI_CEC/SPI[2]_D[0]/GP3[30] AF28 I/O
J2.23 GPMC_A2/SD2_DAT2 CPU.SD2_DAT[2]_SDRWn/GPMC_A[2]/GP2[6] K27 I/O
J2.25 GPMC_A4/SD2_DAT0 CPU.SD2_DAT[0]/GPMC_A[4]/GP1[14] L26 I/O
J2.27 GPMC_A6/CAM_D2 CPU.VOUT[1]_G_Y_YC[0]/CAM_D[2]/PATA_DA[2]/GPMC_A[6]/UART4_TXD/GP0[23] AC18 I/O
J2.29 GPMC_A8/CAM_D0 CPU.VOUT[1]_R_CR[0]/CAM_D[0]/PATA_DA[0]/GPMC_A[8]/UART4_RTSn/GP0[25] AA22 I/O
J2.31 GPMC_A10/CAM_VS CPU.VOUT[1]_B_CB_C[0]/CAM_VS/PATA_IORDY/GPMC_A[10]/UART2_TXD/GP0[27] AD23 I/O
J2.33 VOUT0_FLD/CAM_PCLK/GPMC_A12/GP2_02 CPU.VOUT[0]_FLD/CAM_PCLK/GPMC_A[12]/UART2_RTSn/GP2[02] AF18 I/O
J2.35 3.3V +3V3 - S
J2.37 DGND DGND - G
J2.39 GPMC_A14/I2C2_SDA CPU.VOUT[1]_R_CR[3]/GPMC_A[14]/VIN[1]A_D[22]/HDMI_SDA/SPI[2]_SCLK/I2C[2]_SDA/GP3[21] AG28 I/O
J2.41 GPMC_A16 CPU.GPMC_A[16]/GP2[5] AD27 I/O
J2.43 GPMC_A18 CPU.GPMC_A[18]/TIM2_IO/GP1[13] AE28 I/O
J2.45 GPMC_A20 CPU.GPMC_A[20]/SPI[2]_SCS[1]n/GP1[15] AD28 I/O
J2.47 GPMC_A22 CPU.GPMC_A[22]/SPI[2]_D[1]/HDMI_CEC/TIM4_IO/GP1[17] AB27 I/O
J2.49 VOUT1_G_Y_YC6/GP3_10 CPU.VOUT[1]_G_Y_YC[6]/EMAC[1]_GMTCLK/VIN[1]A_D[11]/PATA_D[3]/GP3[10] AH27 I/O
J2.51 GPMC_CS0n CPU.GPMC_CS[0]n/GP1[23] T28 I/O
J2.53 GPMC_CS2n CPU.GPMC_CS[2]n/GPMC_A[24]/GP1[25] M25 I/O
J2.55 GPMC_CS4n CPU.GPMC_CS[4]n/SD2_CMD/GP1[8] P25 I/O
J2.57 GPMC_WEn CPU.GPMC_WEn U28 O
J2.59 GPMC_ADVn_ALE/GPMC_CS6n CPU.GPMC_ADVn_ALE/GPMC_CS[6]n/TIM5_IO/GP1[28] M26 I/O
J2.61 GPMC_CLK/GPMC_CS5n/GPMC_WAIT1/CLKOUT1 CPU.GPMC_CLK/GPMC_CS[5]n/GPMC_WAIT[1]/CLKOUT1/EDMA_EVT3/TIM4_IO/GP1[27] R26 I/O
J2.63 VOUT1_G_Y_YC8/GP3_12 CPU.VOUT[1]_G_Y_YC[8]/EMAC[1]_MTXD[1]/VIN[1]A_D[13]/PATA_D[5]/GP3[12] AE26 I/O
J2.65 3.3V +3V3 - S
J2.67 DGND DGND - G
J2.69 VOUT1_G_Y_YC9/GP3_13 CPU.VOUT[1]_G_Y_YC[9]/EMAC[1]_MTXD[2]/VIN[1]A_D[14]/PATA_D[6]/GP3[13] AD26 I/O
J2.71 VOUT1_R_CR8/GP3_18 CPU.VOUT[1]_R_CR[8]/EMAC[1]_MTXD[7]/VIN[1]A_D[19]/PATA_D[11]/UART5_RXD/GP3[18] W23 I/O
J2.73 VIN0A_D6/GP2_11 CPU.VIN[0]A_D[6]/GP2[11] AH16 I/O
J2.75 VIN0A_D7/GP2_12 CPU.VIN[0]A_D[7]/GP2[12] AA11 I/O
J2.77 VIN0A_D8_BD0/GP2_13 CPU.VIN[0]A_D[8]_BD[0]/GP2[13] AB15 I/O
J2.79 VIN0A_D9_BD1/GP2_14 CPU.VIN[0]A_D[9]_BD[1]/GP2[14] AG9 I/O
J2.81 VIN0A_D10_BD2/GP2_15 CPU.VIN[0]A_D[10]_BD[2]/GP2[15] AH9 I/O
J2.83 VIN0A_D12_BD4/GP2_17 CPU.VIN[0]A_D[12]_BD[4]/CLKOUT1/GP2[17] AG17 I/O
J2.85 GPMC_BE1n/GPMC_A24/EDMA_EVT1/TIM7_IO/GP1_30 CPU.GPMC_BE[1]n/GPMC_A[24]/EDMA_EVT1/TIM7_IO/GP1[30] V28 I/O
J2.87 SPI3_D1/GP3_16 CPU.VOUT[1]_R_CR[6]/EMAC[1]_MTXD[5]/VIN[1]A_D[17]/PATA_D[9]/SPI[3]_D[1]/GP3[16] AA25 I/O
J2.89 SPI3_D0/GP3_17 CPU.VOUT[1]_R_CR[7]/EMAC[1]_MTXD[6]/VIN[1]A_D[18]/PATA_D[10]/SPI[3]_D[0]/GP3[17] V22 I
J2.91 RSTOUTn CPU.RSTOUTn_WD_OUTn K6 O
J2.93 VIN0A_HSYNC/UART5_RTS CPU.VIN[0]A_HSYNC/UART5_RTSn/GP2[3] AC20 I/O
J2.95 TIM7_IO/GP0_28 CPU.MCA[5]_AXR[1]/MCA[4]_AXR[3]/TIM7_IO/GP0[28] L6 I/O
J2.97 EN_BCK2_LS PMIC.GPIO7 L4 O 3.3V I/O Power Rail Enable
J2.99 SPI3_SCLKGP3_15 CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3[15] AC26 I/O
J2.101 3.3V +3V3 - S
J2.103 DGND DGND - G
J2.105 JTAG_TDI CPU.TDI Y7 I
J2.107 JTAG_TMS CPU.TMS AA7 I/O
J2.109 PORSTn CPU.PORn F1 I
J2.111 SPI3_SCS1n/GP3_14 CPU.VOUT[1]_R_CR[4]/EMAC[1]_MTXD[3]/VIN[1]A_D[15]/SPI[3]_SCS[1]n/GP3[14] AG27 I/O
J2.113 SPI3_D1/UART3_RTSn/GP2_29 CPU.VOUT[1]_HSYNC/EMAC[1]_MCOL/VIN[1]A_VSYNC/PATA_HDDIR/SPI[3]_D[1]/UART3_RTSn/GP2[29 AC24 I/O
J2.115 EMAC0_PHY_LED_LINK/ACT LAN.LED1 3
J2.117 EMAC0_PHY_LED_SPEED LAN.LED2 2
J2.119 SPI3_D0/UART3_CTSn/GP2_30 CPU.VOUT[1]_VSYNC/EMAC[1]_MCRS/VIN[1]A_FLD/VIN[1]A_DE/SPI[3]_D[0]/UART3_CTSn/GP2[30] AA23 I/O
J2.121 UART3_TXD/SD1_SDWP CPU.UART0_DSRn/UART3_TXD/SPI[0]_SCS[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3] AG4 I/O
J2.123 UART3_RTSn CPU.UART0_RIN/UART3_RTSn/UART1_RXD/GP1[5] AF4 I/O
J2.125 VIN1A_D3/GP3_3 CPU.VOUT[1]_B_CB_C[6]/EMAC[1]_MRXD[2]/VIN[1]A_D[3]/UART3_RXD/GP3[3] AD25 I/O
J2.127 ETH_CTTD - -
J2.129 ETH_TX- LAN.TXN 28
J2.131 ETH_TX+ LAN.TXP 29
J2.133 ETH_RX+ LAN.RXP 31
J2.135 ETH_RX- LAN.RXN 30
J2.137 ETH_CTRD - -
J2.139 DGND DGND - G

J2 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J2.2 DGND DGND - G
J2.4 GPMC_D1 CPU.GPMC_D[1]/BTMODE[1] Y28 I/O
J2.6 GPMC_D3 CPU.GPMC_D[3]/BTMODE[3] W27 I/O
J2.8 GPMC_D5 CPU.GPMC_D[5]/BTMODE[5] AA28 I/O
J2.10 GPMC_D7 CPU.GPMC_D[7]/BTMODE[7] V25 I/O
J2.12 SATA_TXP CPU.SATA_TXP0 AB2 O
J2.14 SATA_TXN CPU.SATA_TXN0 AB1 O
J2.16 SATA_RXP CPU.SATA_RXP0 AA1 I
J2.18 SATA_RXN CPU.SATA_RXN0 AA2 I
J2.20 DGND DGND - G
J2.22 GPMC_A1/SD2_DAT3 CPU.SD2_DAT[3]/GPMC_A[1]/GP2[5] J28 I/O
J2.24 GPMC_A3/SD2_DAT1 CPU.SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1[13] M24 I/O
J2.26 GPMC_A5/CAM_D3 CPU.VOUT[1]_G_Y_YC[1]/CAM_D[3]/GPMC_A[5]/UART4_RXD/GP0[22] AD18 I/O
J2.28 GPMC_A7/CAM_D1 CPU.VOUT[1]_R_CR[1]/CAM_D[1]/GPMC_A[7]/UART4_CTSn/GP0[24] AC19 I/O
J2.30 GPMC_A9/CAM_HS CPU.VOUT[1]_B_CB_C[1]/CAM_HS/GPMC_A[9]/UART2_RXD/GP0[26] AE23 I/O
J2.32 GPMC_A11/CAM_FLD/CAM_WEn CPU.VOUT[1]_FLD/CAM_FLD/CAM_WEn/GPMC_A[11]/UART2_CTSn/GP0[28] AB23 I/O
J2.34 GPMC_A13/I2C2_SCL CPU.VOUT[1]_G_Y_YC[2]/GPMC_A[13]/VIN[1]A_D[21]/HDMI_SCL/SPI[2]_SCS[2]n/I2C[2]_SCL/GP3[20] AF27 I/O
J2.36 GPMC_A15 CPU.VOUT[1]_R_CR[2]/GPMC_A[15]/VIN[1]A_D[23]/HDMI_HPDET/SPI[2]_D[1]/GP3[22] AE27 I/O
J2.38 GPMC_A17 CPU.GPMC_A[17]/GP2[6] V23 I/O
J2.40 GPMC_A19 CPU.GPMC_A[19]/TIM3_IO/GP1[14] AC27 I/O
J2.42 GPMC_A21 CPU.GPMC_A[21]/SPI[2]_D[0]/GP1[16] AC28 I/O
J2.44 GPMC_A23 CPU.GPMC_A[23]/SPI[2]_SCLK/HDMI_HPDET/TIM5_IO/GP1[18] AA26 I/O
J2.46 VOUT1_G_Y_YC5/GP3_9 CPU.VOUT[1]_G_Y_YC[5]/EMAC[1]_MRXDV/VIN[1]A_D[10]/PATA_D[2]/GP3[9] AG26 I/O
J2.48 GPMC_CS1n CPU.GPMC_CS[1]n/GPMC_A[25]/GP1[24] K28 I/O
J2.50 GPMC_CS3n CPU.GPMC_CS[3]n/VIN[1]B_CLK/SPI[2]_SCS[0]n/GP1[26] P26 I/O
J2.52 VOUT1_G_Y_YC7/GP3_11 CPU.VOUT[1]_G_Y_YC[7]/EMAC[1]_MTXD[0]/VIN[1]A_D[12]/PATA_D[4]/GP3[11] AF26 I/O
J2.54 DGND DGND - G
J2.56 GPMC_OEn_REn GPMC_OEn_REn T27 O
J2.58 GPMC_BE0n_CLE/GPMC_A25/EDMA_EVT2/TIM6_IO/GP1_29 CPU.GPMC_BE[0]n_CLE/GPMC_A[25]/EDMA_EVT2/TIM6_IO/GP1[29] U27 I/O
J2.60 VIN[0]B_CLK/GP1[9] CPU.VIN[0]B_CLK/CLKOUT0/GP1[9] AE17 I/O (1)
J2.60 VRTC MTR - O (1)
J2.62 VOUT0_R_CR2/GP2_26 CPU.VOUT[0]_R_CR[2]/EMU4/GP2[26] AD9 I/O (1)
J2.62 PLL_1V8 MTR - O (1)
J2.64 VOUT0_R_CR3/GP2_27 CPU.VOUT[0]_R_CR[3]/GP2[27] AB9 I/O (1)
J2.64 CORE_VDD MTR - O (1)
J2.66 GP3_23 CPU.EMAC[0]_MTCLK/VIN[1]B_D[0]/SPI[3]_SCS[3]n/I2C[2]_SDA/GP3[23] L24 I/O (1)
J2.66 VOUT1_G_Y_YC3/GP3_7 CPU.VOUT[1]_G_Y_YC[3]/EMAC[1]_MRXD[6]/VIN[1]A_D[8]/GP3[7] Y23
J2.66 CVDD_ARM MTR - O (1)
J2.68 VOUT1_R_CR9/GP3_19 CPU.VOUT[1]_R_CR[9]/EMAC[1]_MTXEN/VIN[1]A_D[20]/PATA_D[12]/UART5_TXD/GP3[19] Y24 I/O
J2.70 VOUT0_G_Y_YC2/GP2_24 CPU.VOUT[0]_G_Y_YC[2]/EMU3/GP2[24] AH7 I/O
J2.72 VOUT0_G_Y_YC3/GP2_25 CPU.VOUT[0]_G_Y_YC[3]GP2[25] AH15 I/O
J2.74 VOUT0_B_CB_C2/GP2_22 CPU.VOUT[0]_B_CB_C[2]/EMU2/GP2[22] AG7 I/O
J2.76 VOUT0_B_CB_C3/GP2_23 CPU.VOUT[0]_B_CB_C[3]/GP2[23] AE15 I/O
J2.78 MCA2_AFSX/GP0_11 CPU.MCA[2]_AFSX/GP0[11] AA5 I/O (1)
J2.78 CVDD_DSP MTR - O (1)
J2.80 MCA2_ACLKX/GP0_10 CPU.MCA[2]_ACLKX/GP0[10] U6 I/O (1)
J2.80 VDDQ_1V8 MTR - O (1)
J2.82 DGND DGND - G
J2.84 MCA2_AHCLKX/GP0_9 CPU.AUD_CLKIN2/MCA[0]_AXR[9]/MCA[2]_AHCLKX/MCA[5]_AHCLKX/ATL_CLKOUT3/EDMA_EVT2/TIM3_IO/GP0[9] H1 I/O (1)
J2.84 CVDD_HDVICP MTR - O (1)
J2.86 MCA2_AXR0/GP0_12 CPU.MCA[2]_AXR[0]/SD0_DAT[6]/UART5_RXD/GP0[12] N2 I/O (1)
J2.86 DVDD MTR - O (1)
J2.88 MCA2_AXR1/GP0_13 CPU.MCA[2]_AXR[1]/SD0_DAT[7]/UART5_TXD/GP0[13] V6 I/O (1)
J2.88 DVDD_M MTR - O (1)
J2.90 MCA2_AXR2/GP0_14 CPU.MCA[2]_AXR[2]/MCA[1]_AXR[6]/SC0_VPPEN/TIM2_IO/GP0[14] V5 I/O
J2.92 MCA2_AXR3/GP0_15 CPU.MCA[2]_AXR[3]/MCA[1]_AXR[7]/TIM3_IO/GP0[15] H2 I/O
J2.94 JTAG_RTCK CPU.RTCK AD4 I
J2.96 JTAG_TDO CPU.TDO AD4 O
J2.98 JTAG_TCK CPU.TCK AC5 I
J2.100 JTAG_TRSTn CPU.TRSTn AA4 I
J2.102 MRST SV.MR 6 I
J2.104 VIN0A_VSYNC/UART5_CTS CPU.VIN[0]A_VSYNC/UART5_CTSn/GP2[4] AD20 I/O
J2.106 I2C3_SCL CPU.VOUT[1]_B_CB_C[8]/EMAC[1]_MRXD[4]/VIN[1]A_D[5]/I2C[3]_SCL/GP3[5] AH26 I/O
J2.108 I2C3_SDA CPU.VOUT[1]_B_CB_C[9]/EMAC[1]_MRXD[5]/VIN[1]A_D[6]/I2C[3]_SDA/GP3[6] AA24 I/O
J2.110 EMU0 CPU.EMU0 AG8 I/O
J2.112 DEVOSC_WAKE/TIM5_IO/GP1_7 CPU.DEVOSC_WAKE/SPI[1]_SCS[1]n/TIM5_IO/GP1[7] W6 I/O
J2.114 EEPROM_WP EEPROM. I/O
J2.116 DGND DGND - G
J2.118 EMU1 CPU.EMU1 AE11 I/O
J2.120 VIN0A_DE/UART5_TXD CPU.VIN[0]A_DE/VIN[0]B_HSYNC/UART5_TXD/I2C[2]_SDA/GP2[0] AE21 I/O
J2.122 VIN0A_FLD/UART5_RXD CPU.VIN[0]A_FLD/VIN[0]B_VSYNC/UART5_RXD/I2C[2]_SCL/GP2[1] AA20 I/O
J2.124 USBP1 USB1.D+ A, I/O
J2.126 USBM1 USB1.D- A, I/O
J2.128 UART3_RXD/SD1_POW CPU.UART0_DCDn/UART3_RXD/SPI[0]_SCS[3]n/I2C[2]_SCL/SD1_POW/GP1[2] AH4 I/O
J2.130 UART3_CTSn CPU.UART0_DTRn/UART3_CTSn/UART1_TXD/GP1[4] AG2 I/O
J2.132 VIN1A_D4/GP3_4 CPU.VOUT[1]_B_CB_C[7]/EMAC[1]_MRXD[3]/VIN[1]A_D[4]/UART3_TXD/GP3[4] AC25 I/O
J2.134 USBP2 USB2.D+ A, I/O
J2.136 USBM2 USB2.D- A, I/O
J2.138 3.3V +3V3 - S
J2.140 DGND DGND - G

Legend and additional notes[edit | edit source]

(1) Some pins support multiple routing options. Selected option is populated at manufacturing stage and can not be changed at later time.

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