Difference between revisions of "Pinout (Naon)"

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(→‎J1 odd pins (1 to 139))
(→‎J1 even pins (2 to 140))
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==J1 even pins (2 to 140)==
 
==J1 even pins (2 to 140)==
 +
{| class="wikitable" {{table}}
 +
| align="center" style="background:#f0f0f0;"|'''Pin'''
 +
| align="center" style="background:#f0f0f0;"|'''Pin Name'''
 +
| align="center" style="background:#f0f0f0;"|'''Internal Connections'''
 +
| align="center" style="background:#f0f0f0;"|'''Ball/pin #'''
 +
| align="center" style="background:#f0f0f0;"|'''Supply Group'''
 +
| align="center" style="background:#f0f0f0;"|'''Type'''
 +
| align="center" style="background:#f0f0f0;"|'''Voltage'''
 +
| align="center" style="background:#f0f0f0;"|'''Note'''
 +
|-
 +
| J1.2||DGND||DGND||-||||G||||
 +
|-
 +
| J1.4||DGND||DGND||-||||G||||
 +
|-
 +
| J1.6||USB0_DP||CPU.USB0_DP||AG11||||A, I/O||||
 +
|-
 +
| J1.8||UART0_TXD||CPU.UART0_TXD||AG5||||O||1.8V/3.3V||
 +
|-
 +
| J1.10||EEPROM_A0||EEPROM.A1||A1||||O||||
 +
|-
 +
| J1.12||EEPROM_A1||EEPROM.A2||A2||||I/O||||
 +
|-
 +
| J1.14||MDIO_MDIO||CPU.MDIO/GP1[12]||P24||||I/O||||Module mount option
 +
|-
 +
| ||UART4_TXD_GP3_2||CPU.VOUT[1]_B_CB_C[5]/EMAC[1]_MRXD[1]/VIN[1]A_D[2]/UART4_TXD/GP3[2]||AF25||||I/O||||
 +
|-
 +
| J1.16||USB0_VBUS||CPU.USB0_VBUSIN||AG12||||A, I||3.3V||
 +
|-
 +
| J1.18||VIN0A_D13_BD5/CAM_RESET||CPU.VIN[0]A_D[13]_BD[5]/CAM_RESET/GP2[18]||AF17||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.20||VIN0A_D14_BD6/CAM_STROBE||CPU.VIN[0]A_D[14]_BD[6]/CAM_STROBE/GP2[19]||AC12||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.22||VIN0A_D11_BD3/CAM_WEn||CPU.VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[16]||AH17||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.24||VIN0A_D15_BD7/CAM_SHUTTER||CPU.VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/GP2[20]||AC14||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.26||VIN0A_CLK/GP2_2||CPU.VIN[0]A_CLK/GP2[2]||AB20||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.28||DGND||DGND||-||||G||||
 +
|-
 +
| J1.30||VIN0A_D0/GP1_11||CPU.VIN[0]A_D[0]/GP1[11]||AF9||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.32||VIN0A_D1/GP1_12||CPU.VIN[0]A_D[1]/GP1[12]||AB11||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.34||SPI1_SCLK/GP1_17||CPU.SPI[1]_SCLK/GP1[17]||AC3||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.36||VIN0A_D2/GP2_7||CPU.VIN[0]A_D[2]/GP2[7]||AC9||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.38||CAM_D4||CPU.VIN[0]B_FLD/CAM_D[4]/PATA_DIOWn/GP0[21]||AD17||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.40||VIN0A_FLD/CAM_D5||CPU.VIN[0]A_FLD/CAM_D[5]/PATA_CS[0]n/GP0[20]||AC22||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.42||CAM_D6||CPU.VIN[0]B_DE/CAM_D[6]/GP0[19]||AC15||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.44||VIN0A_DE/CAM_D7||CPU.VIN[0]A_DE/CAM_D[7]/GP0[18]||AB17||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.46||VOUT0_R_CR8||CPU.VOUT[0]_R_CR[8]||AE8||||O||1.8V/3.3V||
 +
|-
 +
| J1.48||VOUT0_R_CR6||CPU.VOUT[0]_R_CR[6]||AF6||||O||1.8V/3.3V||
 +
|-
 +
| J1.50||VOUT0_R_CR4||CPU.VOUT[0]_R_CR[4]||AA9||||O||1.8V/3.3V||
 +
|-
 +
| J1.52||DGND||DGND||-||||G||||
 +
|-
 +
| J1.54||VOUT0_G_Y_YC8||CPU.VOUT[0]_G_Y_YC[8]||AE14||||O||1.8V/3.3V||
 +
|-
 +
| J1.56||VOUT0_G_Y_YC6||CPU.VOUT[0]_G_Y_YC[6]||AA8||||O||1.8V/3.3V||
 +
|-
 +
| J1.58||VOUT0_G_Y_YC4||CPU.VOUT[0]_G_Y_YC[4]||AB8||||O||1.8V/3.3V||
 +
|-
 +
| J1.60||VOUT0_B_CB_C8||CPU.VOUT[0]_B_CB_C[8]||AF15||||O||1.8V/3.3V||
 +
|-
 +
| J1.62||VOUT0_B_CB_C6||CPU.VOUT[0]_B_CB_C[6]||AC10||||O||1.8V/3.3V||
 +
|-
 +
| J1.64||VOUT0_B_CB_C4||CPU.VOUT[0]_B_CB_C[4]||AD11||||O||1.8V/3.3V||
 +
|-
 +
| J1.66||VOUT0_AVID/VOUT0_FLD/GP2_21||CPU.VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_SCLK/TIM7_IO/GP2[21]||AA10||||O||1.8V/3.3V||
 +
|-
 +
| J1.68||VOUT0_HSYNC||CPU.VOUT[0]_HSYNC||AC11||||O||1.8V/3.3V||
 +
|-
 +
| J1.70||TIM4_IO/GP0_18||CPU.MCA[3]_AXR[0]/TSI[0]_DATA/TIM4_IO/GP0[18]||G1||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.72||KP_ROW0||KEY.ROW0||23||||I||||
 +
|-
 +
| J1.74||KP_ROW2||KEY.ROW2||1||||I||||
 +
|-
 +
| J1.76||DGND||DGND||-||||G||||
 +
|-
 +
| J1.78||EMAC1_RGMII_RXC||CPU.EMAC[0]_GMTCLK/GPMC_A[6]/SPI[2]_D[1]||K23||||I/O||||Module mount option
 +
|-
 +
| ||KP_ROW5||KEY.ROW5||6||||I||||
 +
|-
 +
| J1.80||EMAC1_RGMII_RXD3||CPU.EMAC[0]_MTXD[0]/GPMC_A[7]/SPI[2]_D[0]||J24||||I/O||||Module mount option
 +
|-
 +
| ||KP_ROW4||KEY.ROW4||5||||I||||
 +
|-
 +
| J1.82||KP_COL0||KEY.COL0||13||||I||||
 +
|-
 +
| J1.84||KP_COL2||KEY.COL2||11||||I||||
 +
|-
 +
| J1.86||EMAC1_RGMII_RXD2||CPU.EMAC[0]_MTXEN/EMAC[1]_RMTXEN/GPMC_A[15]/UART1_RTSn||J23||||I/O||||Module mount option
 +
|-
 +
| ||KP_ROW6||KEY.ROW6||7||||I||||
 +
|-
 +
| J1.88||EMAC1_RGMII_RXD1||CPU.EMAC[0]_MRXDV/GPMC_A[5]/SPI[2]_SCLK||K22||||I/O||||Module mount option
 +
|-
 +
| ||KP_COL5||KEY.COL5||10||||I||||
 +
|-
 +
| J1.90||SPI1_D1/GP1_18||CPU.SPI[1]_D[1]/GP1[18]||AA3||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.92||VIN0A_D22/CAM_D14||CPU.VIN[0]A_D[22]/CAM_D[14]/EMAC[1]_RMTXD[1]/SPI[3]_D[1]/GP0[16]||AC21||||I/O||||
 +
|-
 +
| J1.94||VIN0A_D23/CAM_D15||CPU.VIN[0]A_D[23]/CAM_D[15]/EMAC[1]_RMTXEN/SPI[3]_D[0]/GP0[17]||AC16||||I/O||||
 +
|-
 +
| J1.96||CAN_H||CPU.DCAN0_TX/UART2_TXD/I2C[3]_SDA/GP1[0]||AH6||||I/O||||
 +
|-
 +
| J1.98||CAN_L||CPU.DCAN0_RX/UART2_RXD/I2C[3]_SCL/GP1[1]||AG6||||I/O||||
 +
|-
 +
| J1.100||DGND||DGND||-||||G||||
 +
|-
 +
| J1.102||SD1_DAT6||CPU.SD0_DAT[2]_SDRWn/SD1_DAT[6]/SC1_RST/GP0[5]||Y3||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.104||SD1_DAT7||CPU.SD0_DAT[3]/SD1_DAT[7]/SC1_VCCEN/GP0[6]||Y4||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.106||"EMAC1_RGMII_RXD0
 +
|-
 +
| KP_COL7"||CPU.EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[0]/GPMC_A[13]/UART1_TXD||J22||||I/O||||
 +
|-
 +
| J1.108||EMAC1_RGMII_RXCTL||CPU.EMAC[0]_MRXD[3]/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/UART5_RXD||J25||||I/O||||
 +
|-
 +
| J1.110||EMAC1_RGMII_TXCTL||CPU.EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[0]/GPMC_A[9]/UART4_TXD||H22||||I/O||||
 +
|-
 +
| J1.112||"EMAC1_RGMII_TXD3
 +
|-
 +
| TCLKIN/GP0_30"||CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn||"H24
 +
|-
 +
| T2"||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.114||TIM6_IO/GP0_24||CPU.MCA[4]_AXR[1]/TSI[2]_PACVAL/TIM6_IO/GP0[24]||J4||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.116||VIN0A_D3/GP2_8||CPU.VIN[0]A_D[3]/GP2[8]||AE12||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.118||USB1_DRVVBUS||CPU.AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_AHCLKX/MCA[3]_AHCLKX/ATL_CLKOUT1/ATL_CLKOUT0/VCX_VIC[0]/USB1_DRVVBUS||L5||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.120||VIN0A_D4/GP2_9||CPU.VIN[0]A_D[4]/GP2[9]||AH8||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.122||VIN0A_D5/GP2_10||CPU.VIN[0]A_D[5]/GP2[10]||AG16||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.124||SD0_CLK||CPU.SD0_CLK/GP0[1]||Y6||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.126||DGND||DGND||-||||G||||
 +
|-
 +
| J1.128||SD2_SCLK||CPU.SD2_SCLK/GP1[15]||M23||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.130||SD0_CMD||CPU.SD0_CMD/SD1_CMD/GP0[2]||N1||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.132||VIN1A_D0/GP3_0||CPU.VOUT[1]_B_CB_C[3]/EMAC[1]_MRCLK/VIN[1]A_D[0]/UART4_CTSN/GP3[0]||AH25||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.134||VIN1A_CLK/GP2_31||CPU.VOUT[1]_AVID/EMAC[1]_MRXER/VIN[1]A_CLK/UART4_RTSn/TIM6_IO/GP2[31]||Y22||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.136||HDMI_I2C_SCL||CPU.I2C[1]_SCL/HDMI_SCL||AF24||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.138||HDMI_I2C_SDA||CPU.I2C[1]_SDA/HDMI_SDA||AG24||||I/O||1.8V/3.3V||
 +
|-
 +
| J1.140||DGND||DGND||-||||G||||
 +
|-
 +
|
 +
|}
 +
 
==J2 odd pins (1 to 139)==
 
==J2 odd pins (1 to 139)==
 
==J2 odd pins (1 to 139)==
 
==J2 odd pins (1 to 139)==
 
==Legend and additional notes==
 
==Legend and additional notes==
 
(1) Some pins provide multiple routing options. This means that
 
(1) Some pins provide multiple routing options. This means that

Revision as of 13:57, 31 August 2012

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J1 odd pins (1 to 139)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.1 DGND DGND - G
J1.3 DGND DGND - G
J1.5 USB0_DM CPU.USB0_DM AH11 A, I/O
J1.7 UART0_RXD CPU.UART0_RXD AH5 I
J1.9 VBAT PMIC.VBACKUP D7 S
J1.11 MDIO_MDCLK CPU.MDCLK/GP1[11] H28 I/O (1)
J1.11 UART4_RXD/GP3_1 CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UART4_RXD/GP3[1] AG25 I/O (1)
J1.13 ADC_GND DGND - G
J1.15 ADC0_IN TSC.IN1 16 A
J1.17 USB0_ID CPU.USB0_ID AG10 A I
J1.19 UART0_RTSn/DCAN1_RX CPU.UART0_RTSn/UART4_TXD/DCAN1_RX/SPI[1]_SCS[2]n/SD2_SDCD AF5 I/O
J1.21 UART0_CTSn/DCAN1_TX CPU.UART0_RTSn/UART4_RXD/DCAN1_TX/SPI[1]_SCS[3]n/SD0_SDCD AE6 I/O
J1.23 VIN0A_D16/CAM_D8 CPU.VIN[0]A_D[16]/CAM_D[8]/I2C[2]_SCL/GP0[10] AA21 I/O
J1.25 VIN0A_D17/CAM_D9 CPU.VIN[0]A_D[17]/CAM_D[9]/EMAC[1]_RMRXER/GP0[11] AB21 I/O
J1.27 VIN0A_D18/CAM_D10 CPU.VIN[0]A_D[18]/CAM_D[10]/EMAC[1]_RMRXD[1]/I2C3[3]_SCL/GP0[12] AF20 I/O
J1.29 VIN0A_D19/CAM_D11 CPU.VIN[0]A_D[19]/CAM_D[11]/EMAC[1]_RMRXD[0]/I2C3[3]_SDA/GP0[13] AF21 I/O
J1.31 VIN0A_D20/CAM_D12 CPU.VIN[0]A_D[20]/CAM_D[12]/EMAC[1]_RMCRSDV/SPI[3]_SCS[0]n/GP0[14] AC17 I/O
J1.33 VIN0A_D21/CAM_D13 CPU.VIN[0]A_D[21]/CAM_D[13]/EMAC[1]_RMTXD[0]/SPI[3]_SCLK/GP0[15] AE18 I/O
J1.35 DGND DGND - G
J1.37 SPI1_D0/GP1_26 CPU.SPI[1]_D[0]/GP1[26] AA6 I/O
J1.39 TSC_XP TSC.X+ 2 I Please consider the use of ESD protection devices on carrier board when these pins are connected to actual touch screen.
J1.41 TSC_XM TSC.X- 4 I
J1.43 TSC_YP TSC.Y+ 3 I
J1.45 TSC_YM TSC.Y- 5 I
J1.47 VOUT0_R_CR9 CPU.VOUT[0]_R_CR[9] AC13 O
J1.49 VOUT0_R_CR7 CPU.VOUT[0]_R_CR[7] AF12 O
J1.51 VOUT0_R_CR5 CPU.VOUT[0]_R_CR[5] AF8 O
J1.53 VOUT0_G_Y_YC9 CPU.VOUT[0]_G_Y_YC[9] AF14 O
J1.55 VOUT0_G_Y_YC7 CPU.VOUT[0]_G_Y_YC[7] AD14 O
J1.57 VOUT0_G_Y_YC5 CPU.VOUT[0]_G_Y_YC[5] AB12 O
J1.59 VOUT0_B_CB_C9 CPU.VOUT[0]_B_CB_C[9] AG15 O
J1.61 VOUT0_B_CB_C7 CPU.VOUT[0]_B_CB_C[7] AB10 O
J1.63 DGND DGND - G
J1.65 VOUT0_B_CB_C5 CPU.VOUT[0]_B_CB_C[5] AD15 O
J1.67 TIM2_IO/GP0_8 CPU.AUD_CLKIN1/MCA[0]_AXR[8]/MCA[1]_AHCLKX/MCA[4]_AHCLKX/ATL_CLKOUT2/EDMA_EVT3/TIM2_IO/GP0[8] R5 I/O
J1.69 VOUT0_VSYNC CPU.VOUT[0]_VSYNC AB13 O
J1.71 VOUT0_CLK CPU.VOUT[0]_CLK AD12 O
J1.73 KP_ROW1 KEY.ROW1 24 I
J1.75 KP_ROW3 KEY.ROW3 2 I
J1.77 EMAC1_RGMII_TXD2 CPU.EMAC[0]_MTXD[4]/EMAC[1]_RMRXER/GPMC_A[11]/UART4_RTSn G23 I/O (1)
J1.77 KP_ROW7 KEY.ROW7 8 I (1)
J1.79 EMAC1_RGMII_TXD1 CPU.EMAC[0]_MTXD[1]/GPMC_A[8]/UART4_RXD H25 I/O (1)
J1.79 KP_COL4 KEY.COL4 4 I (1)
J1.81 KP_COL1 KEY.COL1 12 I
J1.83 KP_COL3 KEY.COL3 3 I
J1.85 EMAC1_RGMII_TXD0 CPU.EMAC[0]_MTXD[3]/EMAC[1]_RMRXD[1]/GPMC_A[10]/UART4_CTSn H23 I/O (1)
J1.85 KP_COL6 KEY.COL6 9 I
J1.87 EMAC1_RGMII_TXC CPU.EMAC[0]_MTXD[5]/EMAC[1]_RMCRSDV/GPMC_A[12]/UART1_RXD F27 I/O (1)
J1.87 SPI1_SCS0N/GP1_16 CPU.SPI[1]_SCS[0]n/GP1[16] AD3 I/O
J1.89 DGND DGND G
J1.91 EMAC_REFCLK CPU.EMAC_RMREFCLK/TIM2_IO/GP1[10] J27 I/O
J1.93 USB0_DRVVBUS CPU.USB0_DRVVBUS/GP0[7] AF11 I/O
J1.95 USB1.VBUS CPU.USB1_VBUSIN AG14 A, I
J1.97 HDMI_DP2 CPU.HDMI_DP2 AG21 O
J1.99 HDMI_DN2 CPU.HDMI_DN2 AH21 O
J1.101 HDMI_DP1 CPU.HDMI_DP1 AG20 O
J1.103 HDMI_DN1 CPU.HDMI_DN1 AH20 O
J1.105 HDMI_DP0 CPU.HDMI_DP0 AG19 O
J1.107 HDMI_DN0 CPU.HDMI_DN0 AH19 O
J1.109 HDMI_CLKP CPU.HDMI_CLKP AG18 O
J1.111 HDMI_CLKN CPU.HDMI_CLKN AH18 O
J1.113 DGND DGND G
J1.115 TIM5_IO/GP0_19 CPU.MCA[3]_AXR[1]/TSI[0]_PACVAL/TIM5_IO/GP0[19] G2 I/O
J1.117 VIN1A_HSYNC/GP2_28 CPU.VOUT[1]_CLK/EMAC[1]_MTCLK/VIN[1]A_HSYNC/PATA_HDDIR/GP2[28] AE24 I/O
J1.119 SD1_DAT0 CPU.SD1_DAT[0] P1 I/O
J1.121 SD1_DAT1 CPU.SD1_DAT[1]_SDIRQn P5 I/O
J1.123 SD1_DAT2 CPU.SD1_DAT[2]_SDRWn P4 I/O
J1.125 SD1_DAT3 CPU.SD1_DAT[3] P6 I/O
J1.127 SD1_DAT4 CPU.SD0_DAT[0]/SD1_DAT[4]/SC1_DATA/GP0[3] R7 I/O
J1.129 SD1_DAT5 CPU.SD0_DAT[1]_SDIRQn/SD1_DAT[5]/SC1_CLK/GP0[4] Y5 I/O
J1.131 TV_OUT1 CPU.TV_OUT0 AH24 O
J1.133 TV_OUT2 CPU.TV_OUT1 AH22 O
J1.135 SD1_CMD CPU.SD1_CMD/GP0[0] P2 I/O
J1.137 SD1_CLK CPU.SD1_CLK P3 O
J1.139 DGND DGND - G

J1 even pins (2 to 140)[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Supply Group Type Voltage Note
J1.2 DGND DGND - G
J1.4 DGND DGND - G
J1.6 USB0_DP CPU.USB0_DP AG11 A, I/O
J1.8 UART0_TXD CPU.UART0_TXD AG5 O 1.8V/3.3V
J1.10 EEPROM_A0 EEPROM.A1 A1 O
J1.12 EEPROM_A1 EEPROM.A2 A2 I/O
J1.14 MDIO_MDIO CPU.MDIO/GP1[12] P24 I/O Module mount option
UART4_TXD_GP3_2 CPU.VOUT[1]_B_CB_C[5]/EMAC[1]_MRXD[1]/VIN[1]A_D[2]/UART4_TXD/GP3[2] AF25 I/O
J1.16 USB0_VBUS CPU.USB0_VBUSIN AG12 A, I 3.3V
J1.18 VIN0A_D13_BD5/CAM_RESET CPU.VIN[0]A_D[13]_BD[5]/CAM_RESET/GP2[18] AF17 I/O 1.8V/3.3V
J1.20 VIN0A_D14_BD6/CAM_STROBE CPU.VIN[0]A_D[14]_BD[6]/CAM_STROBE/GP2[19] AC12 I/O 1.8V/3.3V
J1.22 VIN0A_D11_BD3/CAM_WEn CPU.VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[16] AH17 I/O 1.8V/3.3V
J1.24 VIN0A_D15_BD7/CAM_SHUTTER CPU.VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/GP2[20] AC14 I/O 1.8V/3.3V
J1.26 VIN0A_CLK/GP2_2 CPU.VIN[0]A_CLK/GP2[2] AB20 I/O 1.8V/3.3V
J1.28 DGND DGND - G
J1.30 VIN0A_D0/GP1_11 CPU.VIN[0]A_D[0]/GP1[11] AF9 I/O 1.8V/3.3V
J1.32 VIN0A_D1/GP1_12 CPU.VIN[0]A_D[1]/GP1[12] AB11 I/O 1.8V/3.3V
J1.34 SPI1_SCLK/GP1_17 CPU.SPI[1]_SCLK/GP1[17] AC3 I/O 1.8V/3.3V
J1.36 VIN0A_D2/GP2_7 CPU.VIN[0]A_D[2]/GP2[7] AC9 I/O 1.8V/3.3V
J1.38 CAM_D4 CPU.VIN[0]B_FLD/CAM_D[4]/PATA_DIOWn/GP0[21] AD17 I/O 1.8V/3.3V
J1.40 VIN0A_FLD/CAM_D5 CPU.VIN[0]A_FLD/CAM_D[5]/PATA_CS[0]n/GP0[20] AC22 I/O 1.8V/3.3V
J1.42 CAM_D6 CPU.VIN[0]B_DE/CAM_D[6]/GP0[19] AC15 I/O 1.8V/3.3V
J1.44 VIN0A_DE/CAM_D7 CPU.VIN[0]A_DE/CAM_D[7]/GP0[18] AB17 I/O 1.8V/3.3V
J1.46 VOUT0_R_CR8 CPU.VOUT[0]_R_CR[8] AE8 O 1.8V/3.3V
J1.48 VOUT0_R_CR6 CPU.VOUT[0]_R_CR[6] AF6 O 1.8V/3.3V
J1.50 VOUT0_R_CR4 CPU.VOUT[0]_R_CR[4] AA9 O 1.8V/3.3V
J1.52 DGND DGND - G
J1.54 VOUT0_G_Y_YC8 CPU.VOUT[0]_G_Y_YC[8] AE14 O 1.8V/3.3V
J1.56 VOUT0_G_Y_YC6 CPU.VOUT[0]_G_Y_YC[6] AA8 O 1.8V/3.3V
J1.58 VOUT0_G_Y_YC4 CPU.VOUT[0]_G_Y_YC[4] AB8 O 1.8V/3.3V
J1.60 VOUT0_B_CB_C8 CPU.VOUT[0]_B_CB_C[8] AF15 O 1.8V/3.3V
J1.62 VOUT0_B_CB_C6 CPU.VOUT[0]_B_CB_C[6] AC10 O 1.8V/3.3V
J1.64 VOUT0_B_CB_C4 CPU.VOUT[0]_B_CB_C[4] AD11 O 1.8V/3.3V
J1.66 VOUT0_AVID/VOUT0_FLD/GP2_21 CPU.VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_SCLK/TIM7_IO/GP2[21] AA10 O 1.8V/3.3V
J1.68 VOUT0_HSYNC CPU.VOUT[0]_HSYNC AC11 O 1.8V/3.3V
J1.70 TIM4_IO/GP0_18 CPU.MCA[3]_AXR[0]/TSI[0]_DATA/TIM4_IO/GP0[18] G1 I/O 1.8V/3.3V
J1.72 KP_ROW0 KEY.ROW0 23 I
J1.74 KP_ROW2 KEY.ROW2 1 I
J1.76 DGND DGND - G
J1.78 EMAC1_RGMII_RXC CPU.EMAC[0]_GMTCLK/GPMC_A[6]/SPI[2]_D[1] K23 I/O Module mount option
KP_ROW5 KEY.ROW5 6 I
J1.80 EMAC1_RGMII_RXD3 CPU.EMAC[0]_MTXD[0]/GPMC_A[7]/SPI[2]_D[0] J24 I/O Module mount option
KP_ROW4 KEY.ROW4 5 I
J1.82 KP_COL0 KEY.COL0 13 I
J1.84 KP_COL2 KEY.COL2 11 I
J1.86 EMAC1_RGMII_RXD2 CPU.EMAC[0]_MTXEN/EMAC[1]_RMTXEN/GPMC_A[15]/UART1_RTSn J23 I/O Module mount option
KP_ROW6 KEY.ROW6 7 I
J1.88 EMAC1_RGMII_RXD1 CPU.EMAC[0]_MRXDV/GPMC_A[5]/SPI[2]_SCLK K22 I/O Module mount option
KP_COL5 KEY.COL5 10 I
J1.90 SPI1_D1/GP1_18 CPU.SPI[1]_D[1]/GP1[18] AA3 I/O 1.8V/3.3V
J1.92 VIN0A_D22/CAM_D14 CPU.VIN[0]A_D[22]/CAM_D[14]/EMAC[1]_RMTXD[1]/SPI[3]_D[1]/GP0[16] AC21 I/O
J1.94 VIN0A_D23/CAM_D15 CPU.VIN[0]A_D[23]/CAM_D[15]/EMAC[1]_RMTXEN/SPI[3]_D[0]/GP0[17] AC16 I/O
J1.96 CAN_H CPU.DCAN0_TX/UART2_TXD/I2C[3]_SDA/GP1[0] AH6 I/O
J1.98 CAN_L CPU.DCAN0_RX/UART2_RXD/I2C[3]_SCL/GP1[1] AG6 I/O
J1.100 DGND DGND - G
J1.102 SD1_DAT6 CPU.SD0_DAT[2]_SDRWn/SD1_DAT[6]/SC1_RST/GP0[5] Y3 I/O 1.8V/3.3V
J1.104 SD1_DAT7 CPU.SD0_DAT[3]/SD1_DAT[7]/SC1_VCCEN/GP0[6] Y4 I/O 1.8V/3.3V
J1.106 "EMAC1_RGMII_RXD0
KP_COL7" CPU.EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[0]/GPMC_A[13]/UART1_TXD J22 I/O
J1.108 EMAC1_RGMII_RXCTL CPU.EMAC[0]_MRXD[3]/GPMC_A[27]/GPMC_A[26]/GPMC_A[0]/UART5_RXD J25 I/O
J1.110 EMAC1_RGMII_TXCTL CPU.EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[0]/GPMC_A[9]/UART4_TXD H22 I/O
J1.112 "EMAC1_RGMII_TXD3
TCLKIN/GP0_30" CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[1]/GPMC_A[14]/UART1_CTSn "H24
T2" I/O 1.8V/3.3V
J1.114 TIM6_IO/GP0_24 CPU.MCA[4]_AXR[1]/TSI[2]_PACVAL/TIM6_IO/GP0[24] J4 I/O 1.8V/3.3V
J1.116 VIN0A_D3/GP2_8 CPU.VIN[0]A_D[3]/GP2[8] AE12 I/O 1.8V/3.3V
J1.118 USB1_DRVVBUS CPU.AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_AHCLKX/MCA[3]_AHCLKX/ATL_CLKOUT1/ATL_CLKOUT0/VCX_VIC[0]/USB1_DRVVBUS L5 I/O 1.8V/3.3V
J1.120 VIN0A_D4/GP2_9 CPU.VIN[0]A_D[4]/GP2[9] AH8 I/O 1.8V/3.3V
J1.122 VIN0A_D5/GP2_10 CPU.VIN[0]A_D[5]/GP2[10] AG16 I/O 1.8V/3.3V
J1.124 SD0_CLK CPU.SD0_CLK/GP0[1] Y6 I/O 1.8V/3.3V
J1.126 DGND DGND - G
J1.128 SD2_SCLK CPU.SD2_SCLK/GP1[15] M23 I/O 1.8V/3.3V
J1.130 SD0_CMD CPU.SD0_CMD/SD1_CMD/GP0[2] N1 I/O 1.8V/3.3V
J1.132 VIN1A_D0/GP3_0 CPU.VOUT[1]_B_CB_C[3]/EMAC[1]_MRCLK/VIN[1]A_D[0]/UART4_CTSN/GP3[0] AH25 I/O 1.8V/3.3V
J1.134 VIN1A_CLK/GP2_31 CPU.VOUT[1]_AVID/EMAC[1]_MRXER/VIN[1]A_CLK/UART4_RTSn/TIM6_IO/GP2[31] Y22 I/O 1.8V/3.3V
J1.136 HDMI_I2C_SCL CPU.I2C[1]_SCL/HDMI_SCL AF24 I/O 1.8V/3.3V
J1.138 HDMI_I2C_SDA CPU.I2C[1]_SDA/HDMI_SDA AG24 I/O 1.8V/3.3V
J1.140 DGND DGND - G

J2 odd pins (1 to 139)[edit | edit source]

J2 odd pins (1 to 139)[edit | edit source]

Legend and additional notes[edit | edit source]

(1) Some pins provide multiple routing options. This means that

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