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Contents
IntroductionEdit
This chapter contains the pinout description of the Axel Ultra module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Axel Ultra connectors.
Each row in the pinout tables contains the following information:
- Pin: reference to the connector pin
- Pin Name: pin (signal) name on the Axel Ultra connectors
- Internal connections: connections to the Axel Ultra components
- CPU.<x> : pin connected to CPU pad named <x>
- CAN.<x> : pin connected to the CAN transceiver
- PMIC.<x> : pin connected to the Power Manager IC
- LAN.<x> : pin connected to the LAN PHY
- NOR.<x>: pin connected to the flash NOR
- SV.<x>: pin connected to voltage supervisor
- MTR: pin connected to voltage monitors
- Ball/pin #: Component ball/pin number connected to signal
- Supply Group: Power Supply Group
- Type: pin type
- I = Input
- O = Output
- D = Differential
- Z = High impedance
- S = Power supply voltage
- G = Ground
- A = Analog signal
- Voltage: I/O voltage levels
J1 odd pins (1 to 139)Edit
| Pin | Pin Name | Internal Connections | Ball/pin # |
| J1.1 | DGND | DGND | |
| J1.3 | DI0_DISP_CLK | CPU.DI0_DISP_CLK | N19 |
| J1.5 | DI0_PIN2 | CPU.DI0_PIN2 | N25 |
| J1.7 | DI0_PIN3 | CPU.DI0_PIN3 | N20 |
| J1.9 | DI0_PIN4 | CPU.DI0_PIN4 | P25 |
| J1.11 | DI0_PIN15 | CPU.DI0_PIN15 | N21 |
| J1.13 | DISP0_DAT0 | CPU.DISP0_DAT0 | P24 |
| J1.15 | DISP0_DAT1 | CPU.DISP0_DAT1 | P22 |
| J1.17 | DISP0_DAT2 | CPU.DISP0_DAT2 | P23 |
| J1.19 | DISP0_DAT3 | CPU.DISP0_DAT3 | P21 |
| J1.21 | DGND | DGND | |
| J1.23 | DISP0_DAT4 | CPU.DISP0_DAT4 | P20 |
| J1.25 | DISP0_DAT5 | CPU.DISP0_DAT5 | R25 |
| J1.27 | DISP0_DAT6 | CPU.DISP0_DAT6 | R23 |
| J1.29 | DISP0_DAT7 | CPU.DISP0_DAT7 | R24 |
| J1.31 | DISP0_DAT8 | CPU.DISP0_DAT8 | R22 |
| J1.33 | DISP0_DAT9 | CPU.DISP0_DAT9 | T25 |
| J1.35 | DISP0_DAT10 | CPU.DISP0_DAT10 | R21 |
| J1.37 | DISP0_DAT11 | CPU.DISP0_DAT11 | T23 |
| J1.39 | DISP0_DAT12 | CPU.DISP0_DAT12 | T24 |
| J1.41 | DGND | DGND | |
| J1.43 | DISP0_DAT13 | CPU.DISP0_DAT13 | R20 |
| J1.45 | DISP0_DAT14 | CPU.DISP0_DAT14 | U25 |
| J1.47 | DISP0_DAT15 | CPU.DISP0_DAT15 | T22 |
| J1.49 | DISP0_DAT16 | CPU.DISP0_DAT16 | T21 |
| J1.51 | DISP0_DAT17 | CPU.DISP0_DAT17 | U24 |
| J1.53 | DISP0_DAT18 | CPU.DISP0_DAT18 | V25 |
| J1.55 | DISP0_DAT19 | CPU.DISP0_DAT19 | U23 |
| J1.57 | DISP0_DAT20 | CPU.DISP0_DAT20 | U22 |
| J1.59 | DISP0_DAT21 | CPU.DISP0_DAT21 | T20 |
| J1.61 | DGND | DGND | |
| J1.63 | DISP0_DAT22 | CPU.DISP0_DAT22 | V24 |
| J1.65 | DISP0_DAT23 | CPU.DISP0_DAT23 | W24 |
| J1.67 | WD_SET0 | WDT.SET0 | |
| J1.69 | WD_SET1 | WDT.SET0 | |
| J1.71 | WD_SET2 | WDT.SET0 | |
| J1.73 | USB_OTG_CHDN | CPU.USB_OTG_CHDN | B8 |
| J1.75 | USB_OTG_VBUS | CPU.USB_OTG_VBUS | E9 |
| J1.77 | USB_OTG_DN | CPU.USB_OTG_DN | B6 |
| J1.79 | USB_OTG_DP | CPU.USB_OTG_DP | A6 |
| J1.81 | DGND | DGND | |
| J1.83 | USB_HOST_DP | CPU.USB_HOST_DP | E10 |
| J1.85 | USB_HOST_DN | CPU.USB_HOST_DN | F10 |
| J1.87 | USB_H1_VBUS | CPU.USB_H1_VBUS | D10 |
| J1.89 | SD1_DAT0 | CPU.SD1_DAT0 | A21 |
| J1.91 | SD1_DAT1 | CPU.SD1_DAT1 | C20 |
| J1.93 | SD1_DAT2 | CPU.SD1_DAT2 | E19 |
| J1.95 | SD1_DAT3 | CPU.SD1_DAT3 | F18 |
| J1.97 | SD1_CMD | CPU.SD1_CMD | B21 |
| J1.99 | SD1_CLK | CPU.SD1_CLK | D20 |
| J1.101 | DGND | DGND | |
| J1.103 | SW2_1.8V/3.3V | ??? | |
| J1.105 | ETH0_LED1 | LAN.LED1/PME_N1 | 17 |
| J1.107 | ETH0_LED2 | LAN.LED2 | 15 |
| J1.109 | DGND | DGND | |
| J1.111 | ETH0_TXRX0_M | LAN.TXRXM_A | 3 |
| J1.113 | ETH0_TXRX0_P | LAN.TXRXP_A | 2 |
| J1.115 | DGND | DGND | |
| J1.117 | ETH0_TXRX1_M | LAN.TXRXM_B | 6 |
| J1.119 | ETH0_TXRX1_P | LAN.TXRXP_B | 5 |
| J1.121 | DGND | DGND | |
| J1.123 | ETH0_TXRX2_M | LAN.TXRXM_C | 8 |
| J1.125 | ETH0_TXRX2_P | LAN.TXRXP_C | 7 |
| J1.127 | DGND | DGND | |
| J1.129 | ETH0_TXRX3_M | LAN.TXRXM_D | 11 |
| J1.131 | ETH0_TXRX3_P | LAN.TXRXP_D | 10 |
| J1.133 | DGND | DGND | |
| J1.135 | RGMII_MDC | CPU.ENET_MDC | V20 |
| J1.137 | RGMII_MDIO | CPU.ENET_MDIO | V23 |
| J1.139 | PMIC_VSNVS | CPU.VDD_SNVS_IN | G11 |