Bureaucrats, dave_user, Administrators
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→External pull-ups
= External pull-ups =
* PROGRAM_B: UG-585 indicates to use a 4.7kΩ pull-up resistor. This value was not known when the Xilinx Zynq 7000 family was released. Nevertheless, for a stronger pull-up, as indicated in the UG-585, place an external pull-up to a 3.3V controlled power domain in order to put it in parallel with the internal 10kΩ pull-up.
* INIT_B: for using this signal as ''PL initializing signal Low-to-High transition'', place an external pull-up to a 3.3V controlled power domain.
"3.3V controlled power domain" means that this domain has to be designed in order to meet the power sequences described [[Power (Bora/BoraLite)|here]]. Typically, this is achieved by using a cheap power switch that is enabled by the BOARD_PGOOD signal as illustrated in the following example:
Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage. The input of that switch is connected to the 3.3V rail used to power the SOM itself. Also, that switch is configured in order to have a 654μs delay. Thus, the The external switch shown in the picture does not have to enable before the internal switch. In other wordsThus, its delay has not to be less than 654μs.
