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PL initialization signals (Bora/BoraX/BoraLite)

8 bytes added, 15:42, 14 December 2020
External pull-ups
Please, take into account that a similar switch is used on the SOM to generate the VCCO_0 voltage. The input of that switch is connected to the 3.3V rail used to power the SOM itself. This Also, that switch is configured in order to have a 654us 654μs delay. Thus, the external switch shown in the picture does not have to enable before the internal switch. In other words, its delay has not to be less than 654us654μs.
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