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J2 J7 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
== Introduction ==
JTAG signals are routed to a dedicated connector (J2J7) on the BORA Axel Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
[[File:BORAliteAxellite-jtag-conn.png|500px|frameless|border]]
== J2 J7 - Connector's pinout ==
{| class="wikitable"
|5 || JTAG_TDI || - || -
|-
|6 || FPGA_INIT_B JTAG_nTRST || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|7 || FPGA_PROGRAM_B CPU_PORn || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|8 || FPGA_DONE N.C. || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|9 || N.C. || - || -
|-
|10 || 3V3 JTAG_VREF || - || 3.3VIN enabled with BOARD_PGOOD-
|-
|}
