Changes

JTAG signals are routed to a dedicated connector (J7J2) on the Axel BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).

[[File:AxelliteBORAlite-jtag-conn.png|500px|frameless|border]]

== J7 J2 - Connector's pinout ==

J7 J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:

|6 || JTAG_nTRST FPGA_INIT_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|7 || CPU_PORn FPGA_PROGRAM_B || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|8 || N.C. FPGA_DONE || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]

|10 || JTAG_VREF 3V3 || - || -3.3VIN enabled with BOARD_PGOOD