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{{AppliesToAxelLite}}
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{{ObsoleteWikiPage|link=AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/JTAG}}
== Introduction ==
JTAG signals are routed to a dedicated connector (J2J7) on the BORA Axel Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
[[File:BORAliteAxellite-jtag-conn.png|500px|frameless|border]]
== J2 J7 - Connector's pinout ==
{| class="wikitable"
|2 || JTAG_TCK || - || -
|-
|3 || JTAG_TMS || - || 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
|-
|4 || JTAG_TDO || - || 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
|-
|5 || JTAG_TDI || - || 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
|-
|6 || FPGA_INIT_B JTAG_nTRST || - || Place external 4.7 kO (or stronger) 10K pull-up resistor to 3V3 (BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]signal)
|-
|7 || FPGA_PROGRAM_B CPU_PORn || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|8 || FPGA_DONE N.C. || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supply For more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
|-
|9 || N.C. || - || -
|-
|10 || 3V3 JTAG_VREF || - || 3.3VIN enabled with 3V3 (BOARD_PGOODdriven signal)
|-
|}