JTAG signals are routed to a dedicated connector (J2J7) on the BORA Axel Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
|6 || FPGA_INIT_B JTAG_nTRST || - || Place external 4.7 kO (or stronger) 10K pull-up resistor to 3V3 (BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]signal)
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|7 || FPGA_PROGRAM_B CPU_PORn || - || Place external 4.7 kO (or stronger) pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]
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|8 || FPGA_DONE N.C. || - || Place external 300O pull-up resistor to BOARD_PGOOD driven +3.3V supplyFor more details please refer to Table 2-4 on [http://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 7 Series FPGAs Configuration]