Difference between revisions of "ORCA SOM/ORCA Hardware/Power and Reset/System boot"
< ORCA SOM | ORCA Hardware
(Tag: Visual edit) |
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* once it is satisfied, it executes the boot code | * once it is satisfied, it executes the boot code | ||
== Boot options == | == Boot options == | ||
| + | {| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;" | ||
| + | | [[File:TBD.png|30px]] | ||
| + | | '''Section not completed yet''' | ||
| + | |} | ||
| + | |||
| − | Many options are available related | + | Many options are available related for ORCA SOM System boot. They are selected by the BOOT_MODE[0..2] signals as reported in the following table: |
{| class="wikitable" | {| class="wikitable" | ||
!BOOT_MODE_2 | !BOOT_MODE_2 | ||
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When the signals are left floating the primary boot device is set by default to eMMC on SD3. | When the signals are left floating the primary boot device is set by default to eMMC on SD3. | ||
| − | The | + | The BOOT_MODE[0..2] signals are latched when processor reset is released. |
| − | + | The boot process is managed by on-chip boot ROM code: please refer to the processor's Reference Manual for more information. | |
---- | ---- | ||
[[Category:ORCA]] | [[Category:ORCA]] | ||
Revision as of 14:15, 22 February 2021
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System boot[edit | edit source]
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot options[edit | edit source]
|
Section not completed yet |
Many options are available related for ORCA SOM System boot. They are selected by the BOOT_MODE[0..2] signals as reported in the following table:
| BOOT_MODE_2 | BOOT_MODE_1 | BOOT_MODE_0 | BOOT peripheral |
|---|---|---|---|
| 0 | 0 | 0 | Boot From Internal Fuses |
| 0 | 0 | 1 | USB Serial Download |
| 0 | 1 | 0 | USDHC3 (eMMC boot only, SD3 8-bit) |
| 0 | 1 | 1 | USDHC2 (SD boot only, SD2) |
| 1 | 0 | 0 | NAND 8-bit single device 256 page |
| 1 | 0 | 1 | NAND 8-bit single device 512 page |
| 1 | 1 | 0 | QSPI 3B Read |
When the signals are left floating the primary boot device is set by default to eMMC on SD3.
The BOOT_MODE[0..2] signals are latched when processor reset is released.
The boot process is managed by on-chip boot ROM code: please refer to the processor's Reference Manual for more information.
