<section begin="History" />
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|-|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD|-|! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|...2023/11/08|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...|! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fbededed; padding:5px; color:#000000"|...Update information on PMIC_ON_REQ and software reset
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<section end="History" /><section begin="Body" />
== Reset scheme and control signals ==
[[File:ORCA-reset-scheme.png | 800px]]
=== NVCC_VSNVS_1V8 ===Some signals that are related to reset circuitry are pulled-up to NVCC_VSNVS_1V8 (1.8V internal rail). Hence ''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:'it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level.''' === PMIC_RST_B ===EXT_RESET is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. Connect EXT_RESET signal to GND (for example with a button or an open-collector circuit) causes the PMIC to assert its POR_B output. When this signal is pulled low all the power supplies except for the SNVS domain will be OFF.
* MRST* POR* SNVS* SYSRST* The RESETn will keep asserted for 250 ms after PMIC_RST_B is released, thus providing enough time for the power supplies to be completely powered down.During this time, the CPU_PORb driven by the PMIC will also keep asserted (low)..'''
'''TBD: indicare le connessioni del segnale di After RESETn is released, the power supplies will start to ramp up in defined sequence. When all the power supplies have reached their operating voltages, POR_B will be de-asserted, and the CPU may begin booting from reset verso altri device interni (come per esempio la NOR SPI'''.
''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''=== PMIC_ON_REQ//VMON_RST ===Two different routing options are available for this pin.
=== PMIC_VSNVS ===Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in case of AxelLite this pin is connected to 3.3VIN power rail* voltage applied to PMICS's LICELL pin** in case of AxelLite By default, this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configurationPMIC_ON_REQ signal.Hence '''it The PMIC_ON_REQ signal is recommended that driven by iMX8MPlus SoC to place the system designer takes into account these factors in order to properly manage these signals at carrier board level'''power-down mode.
Optionally, PMIC_ON_REQ//VMON_RST can be routed to the master reset input of a voltage supervisor instead. For more details about this option, please refer write to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' documentthe [mailto:sales@dave.eu Sales Department].
=== CPU_PORn ===
PMIC can assert this active-low signal. Other internal IC, such as ethernet PHY or boot memory devices, could be connected to this signal. This guarantees that they are in a known state when reset signal is released.
=== CPU_ONOFF ===
CPU_ONOFF is internally pulled-up with a 100kΩ to NVCC_VSNVS_1V8. This input signal is connected directly to the ONOFF input of the CPU.
The following devices can assert this active-low signal:=== BOARD_PGOOD ===* PMIC* multiple-BOARD_PGOOD is the output of the voltage monitor: this device monitors critical on the internal NVCC_3V3 rail (I/O pins supply) and must be used as power voltages and triggers a reset pulse in case any of these exhibits a brownout condition enable for all the electronics on MITO 8M carrier board.
Since SPI NOR flash can be used as boot device, CPU_PORn When the I/O pins power rail on MITO 8M is not ready (BOARD_PGOOD low) all the integrated circuits connected to this device too. This guarantees it is the CPU must be powered off in order to avoid back-powering or other issue related to a known state when reset signal is releasedwrong power-up sequence.
=== BOOT_MODE_[0-2] ===
BOOT_MODE_x pins can be internally pulled-up with 10kΩ to NVCC_3V3 or pulled-down with 10kΩ to DGND to provide the default boot mode. The previous block diagram shows the SD3 eMMC boot option.
=== Handling CPUTo overwrite the boot configuration these pins can be pulled low or high with 1kΩ resistor, the pull-initiated software reset ==='''By default, MX6 processor does not assert any external signal when it initiates up rail has to be a software reset sequence3. Also default software reset implementation does not guarantee that all processor registers are reset properly'''3V enabled by BOARD_PGOOD signal.
For these reasons, it === WDOG_B ===WDOG_B is strongly recommended to use a different approach PMIC input signal that, in combination with the use of is configured by default to generate a system reset. It is internally connected to processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issuedoutput.
=== Handling CPU-initiated software reset ===By default, ORCA SOM implements a conservative approach regarding CPU-initiated software reset. In essence, whenever a software reset is issued, a full power-up cycle is triggered. This technique is implemented in [[ORCA_SOM/DESK-iMX8MPlusMX8M-L | DESK-MX8M-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of processora SOC's WDT #2 to assert the WDOG2_B WDOG1_WDOG_B reset signal. This signal in turn is routed to GPIO_1 GPIO1_IO02 pad (MUX mode = 1, ''internal connection only''). At the hardware level, this signal is AC-coupled connected to a 3-state output buffer (please refer the PMIC WDOG_B input to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRONachieve the desired outcome.
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[[Category:ORCA]]