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ORCA SOM/ORCA Hardware/Pinout Table

1,498 bytes added, 15:49, 8 November 2023
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 14728|Jan 2021/10/01}}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First documentation release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/11/08
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Update information on PMIC_ON_REQ and software reset
|-
|}<section end="History" /><section begin="Body" />
==Connectors and Pinout Table==
|NVCC_SNVS_1V8
|I/O
|optionally connected tovoltage monitor resetmore information on [[ORCA_SOM/ORCA_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PMIC_ON_REQ.2F.2FVMON_RST | Reset scheme]] page
|
|
|-
|J1.171
|USB2_IDDNU|CPU.USB2_IDDNU|E12-|NVCC_3V3-|I-|DNU stands for Do Not Use. This pin must be left unconnected/floating.
|
|
|-
|J1.191
|USB1_IDETH0_INTn|CPOULAN.USB1_IDINT_N/PME_N2|B1138|NVCC_3V3VDD_1V8|IO|Must be level translated if used @ 3V3Internally pulled-up to 1.8V
|
|
|GPIO2_IO[7]
|-
| rowspan="56" |J1.32| rowspan="56" |SD1_DATA6| rowspan="56" |CPU.SD1_DATA6| rowspan="56" |AA28| rowspan="56" |NVCC_3V3| rowspan="56" |I/O| rowspan="56" |
|Pin ALT-0
|USDHC1_DATA6
|-
|Pin ALT-1
|ENET1_RGMII_RX_CTLFLEXSPI_B_DATA[2]|-|Pin ALT-2|USDHC3_DATA2
|-
|Pin ALT-3
|I2C2_SCLFLEXSPI_A_DATA[6]
|-
|Pin ALT-4
|UART3_TXISP_PRELIGHT_TRIG_1
|-
|Pin ALT-5
|GPIO2_IOGPIO3_IO[812]
|-
| rowspan="5" |J1.34
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_EXT_CLK
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_IN
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_OUT
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_MCLK
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_BCLK
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_DATA[0]
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_SYNC
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_BCLK
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_DATA[0]
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |TBDHardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_SYNC
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |optionally connectedHardware mounting option depending on order code to SE ISO_14443_LA pinSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[0]
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |optionally connectedHardware mounting option depending on order code to SE ISO_14443_LB pinSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[1]
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |optionally connectedHardware mounting option depending on order code to SE ISO_7816_CLK pinSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[2]
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |optionally connected to SEHardware mounting option depending on order codeSAI5 or SE050 ISO 7816 RST_N pin(**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[3]
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |optionally connectedHardware mounting option depending on order code to SE enable pinSAI5 or SE050 (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_SYNC
|-
|}
'''(*)''' SPIDF and ISP signals cannot be present at the same time. ISP signals are in alternative to NAND and eMMC usage (see i.MX8Plus NAND controller on Reference Manual for more details). Please contact [mailto:sales@dave.eu sales] for more information
'''(**)''' SAI5 and SE050 ISO interface cannot be present at the same time. Please contact [mailto:sales@dave.eu sales] for more information
----
[[Category:ORCA]]
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