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ORCA SOM/ORCA Hardware/Pinout Table

2,433 bytes added, 15:49, 8 November 2023
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|-
|}
<section end="History" /><section begin="Body" />''TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM'' ''TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins'' '''TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)'''
==Connectors and Pinout Table==
=== Connectors description ===
In the following table are described all available connectors integrated on [[ORCASOM]]:
{| class="wikitable"
|-
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA pinout specifications. See the images below for reference:
[[File:ORCA-top-pin1-259.png|500px|thumb|ORCA TOP view|none]][[File:ORCA-bottom-pin2-260.png|500px|thumb|ORCA BOTTOM view|none]]
===Pinout table naming conventions ===
This chapter contains the pinout description of the ORCA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' 260-pin DDR4 SO-DIMM ORCA connector.
Each row in the pinout tables contains the following information:
* NAND.<x>: pin connected to the flash NAND
* MTR: pin connected to voltage monitors
* TPMSE: pin connected to TPM Secure Element unit <code>SE050</code>
|-
|'''Ball/pin #'''
|NVCC_SNVS_1V8
|I/O
|optionally connected tovoltage monitor resetmore information on [[ORCA_SOM/ORCA_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PMIC_ON_REQ.2F.2FVMON_RST | Reset scheme]] page
|
|
|G10
|NVCC_3V3
|TBDI
|internal 10k pull-up or pull-down
according to specific model
|F8
|NVCC_3V3
|TBDI
|internal 10k pull-up or pull-down
according to specific model
|G8
|NVCC_3V3
|TBDI
|internal 10k pull-up or pull-down
according to specific model
|-
|J1.171
|USB2_IDDNU|CPU.USB2_IDDNU|E12-|NVCC_3V3-|I-|DNU stands for Do Not Use. This pin must be left unconnected/floating.
|
|
|-
|J1.191
|USB1_IDETH0_INTn|CPOULAN.USB1_IDINT_N/PME_N2|B1138|NVCC_3V3VDD_1V8|IO|Must be level translated if used @ 3V3Internally pulled-up to 1.8V
|
|
| rowspan="5" |J1.16
| rowspan="5" |SD1_CLK
| rowspan="5" |CPU.SD1_CLK| rowspan="5" |TBDW28| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.18
| rowspan="5" |SD1_CMD
| rowspan="5" |CPU.SD1_CMD| rowspan="5" |TBDW29| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.20
| rowspan="5" |SD1_DATA0
| rowspan="5" |CPU.SD1_DATA0| rowspan="5" |TBDY29| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.22
| rowspan="5" |SD1_DATA1
| rowspan="5" |CPU.SD1_DATA1| rowspan="5" |TBDY28| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.24
| rowspan="5" |SD1_DATA2
| rowspan="5" |CPU.SD1_DATA2| rowspan="5" |TBDV29| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.26
| rowspan="5" |SD1_DATA3
| rowspan="5" |CPU.SD1_DATA3| rowspan="5" |TBDV28| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.28
| rowspan="5" |SD1_DATA4
| rowspan="5" |CPU.SD1_DATA4| rowspan="5" |TBDU26| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.30
| rowspan="5" |SD1_DATA5
| rowspan="5" |CPU.SD1_DATA5| rowspan="5" |TBDAA29| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="6" |J1.32
| rowspan="6" |SD1_DATA6
| rowspan="6" |CPU.SD1_DATA6| rowspan="6" |TBDAA28| rowspan="6" |NVCC_SD1NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |
| rowspan="5" |J1.34
| rowspan="5" |SD1_DATA7
| rowspan="5" |CPU.SD1_DATA7| rowspan="5" |TBDU25| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.36
| rowspan="5" |SD1_RESET_B
| rowspan="5" |CPU.SD1_RESET_B| rowspan="5" |TBDW25| rowspan="5" |NVCC_SD1NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="4" |J1.38
| rowspan="4" |SD1_STROBE
| rowspan="4" |CPU.SD1_STROBE| rowspan="4" |TBDW26| rowspan="4" |NVCC_SD1NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
| rowspan="2" |J1.42
| rowspan="2" |SD2_CD_B
| rowspan="2" |CPU.SD2_CD_B| rowspan="2" |TBDAD29| rowspan="2" |NVCC_SD2NVCC_3V3
| rowspan="2" |I/O
| rowspan="2" |
| rowspan="4" |J1.44
| rowspan="4" |SD2_CLK
| rowspan="4" |CPU.SD2_CLK| rowspan="4" |TBDAB29| rowspan="4" |NVCC_SD2NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |
| rowspan="5" |J1.46
| rowspan="5" |SD2_CMD
| rowspan="5" |CPU.SD2_CMD| rowspan="5" |TBDAB28| rowspan="5" |NVCC_SD2NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.48
| rowspan="5" |SD2_DATA0
| rowspan="5" |CPU.SD2_DATA0| rowspan="5" |TBDAC28| rowspan="5" |NVCC_SD2NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.50
| rowspan="5" |SD2_DATA1
| rowspan="5" |CPU.SD2_DATA1| rowspan="5" |TBDAC29| rowspan="5" |NVCC_SD2NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="5" |J1.52
| rowspan="5" |SD2_DATA2
| rowspan="5" |CPU.SD2_DATA2| rowspan="5" |TBDAA26| rowspan="5" |NVCC_SD2NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |
| rowspan="6" |J1.54
| rowspan="6" |SD2_DATA3
| rowspan="6" |CPU.SD2_DATA3| rowspan="6" |TBDAA25| rowspan="6" |NVCC_SD2NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |
| rowspan="3" |J1.56
| rowspan="3" |SD2_RESET_B
| rowspan="3" |CPU.SD2_RESET_B| rowspan="3" |TBDAD28| rowspan="3" |NVCC_SD2NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
| rowspan="3" |J1.58
| rowspan="3" |SD2_WP
| rowspan="3" |CPU.SD2_WP| rowspan="3" |TBDAC26| rowspan="3" |NVCC_SD2NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |
NOR on board)
|SD2_WP
|CPU.SD2_WP|TBDAC26|NVCC_SD2NVCC_3V3
|O
|internal use for
|J1.62
|CLKIN1
|CPU.CLKIN1|TBDK28
|NVCC_3V3
|I
|J1.64
|CLKIN2
|CPU.CLKIN2|TBDL28
|NVCC_3V3
|I
|J1.68
|CLKOUT1
|CPU.CLKOUT1|TBDK29
|NVCC_3V3
|O
|J1.70
|CLKOUT2
|CPU.CLKOUT2|TBDL29
|NVCC_3V3
|O
| rowspan="4" |J1.74
| rowspan="4" |HDMI_CEC
| rowspan="4" |CPU.HDMI_CEC| rowspan="4" |TBDAD22
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.76
| rowspan="4" |HDMI_DDC_SCL
| rowspan="4" |CPU.HDMI_DDC_SCL| rowspan="4" |TBDAC22
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.78
| rowspan="4" |HDMI_DDC_SDA
| rowspan="4" |CPU.HDMI_DDC_SDA| rowspan="4" |TBDAF22
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="5" |J1.80
| rowspan="5" |HDMI_HPD
| rowspan="5" |CPU.HDMI_HPD| rowspan="5" |TBDAE22
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
|J1.84
|HDMI_TXC_N
|CPU.HDMI_TXC_N|TBDAJ24
| -
|D
|J1.86
|HDMI_TXC_P
|CPU.HDMI_TXC_P|TBDAH24
| -
|D
|J1.88
|HDMI_TX0_N
|CPU.HDMI_TX0_N|TBDAJ25
| -
|D
|J1.90
|HDMI_TX0_P
|CPU.HDMI_TX0_P|TBDAH25
| -
|D
|J1.92
|HDMI_TX1_N
|CPU.HDMI_TX1_N|TBDAJ26
| -
|D
|J1.94
|HDMI_TX1_P
|CPU.HDMI_TX1_P|TBDAH26
| -
|D
|J1.96
|HDMI_TX2_N
|CPU.HDMI_TX2_N|TBDAJ27
| -
|D
|J1.98
|HDMI_TX2_P
|CPU.HDMI_TX2_P|TBDAH27
| -
|D
|J1.102
|EARC_P_UTIL
|CPU.EARC_P_UTIL|TBDAJ23
|VDDA_1V8
|D
|J1.104
|EARC_N_HPD
|CPU.EARC_N_HPD|TBDAH22
|VDDA_1V8
|D
|J1.106
|EARC_AUX
|CPU.EARC_AUX|TBDAH23
|VDDA_1V8
|I/O
| rowspan="5" |J1.110
| rowspan="5" |ECSPI1_MISO
| rowspan="5" |CPU.ECSPI1_MISO| rowspan="5" |TBDAD20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.112
| rowspan="5" |ECSPI1_MOSI
| rowspan="5" |CPU.ECSPI1_MOSI| rowspan="5" |TBDAC20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.114
| rowspan="5" |ECSPI1_SCLK
| rowspan="5" |CPU.ECSPI1_SCLK| rowspan="5" |TBDAF20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.116
| rowspan="5" |ECSPI1_SS0
| rowspan="5" |CPU.ECSPI1_SS0| rowspan="5" |TBDAE20
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="6" |J1.120
| rowspan="6" |ECSPI2_MISO
| rowspan="6" |CPU.ECSPI2_MISO| rowspan="6" |TBDAH20
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="5" |J1.122
| rowspan="5" |ECSPI2_MOSI
| rowspan="5" |CPU.ECSPI2_MOSI| rowspan="5" |TBDAJ21
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.124
| rowspan="5" |ECSPI2_SCLK
| rowspan="5" |CPU.ECSPI2_SCLK| rowspan="5" |TBDAH21
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.126
| rowspan="5" |ECSPI2_SS0
| rowspan="5" |CPU.ECSPI2_SS0| rowspan="5" |TBDAJ22
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="4" |SPDIF_EXT_CLK//
ISP_FL_TRIG_0
| rowspan="4" |CPU.SPDIF_EXT_CLK| rowspan="4" |TBDAC18
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_EXT_CLK
| rowspan="6" |SPDIF_RX//
ISP_SHUTTER_TRIG_0
| rowspan="6" |CPU.SPDIF_RX| rowspan="6" |TBDAD18
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_IN
| rowspan="6" |SPDIF_TX//
ISP_FLASH_TRIG_0
| rowspan="6" |CPU.SPDIF_TX| rowspan="6" |TBDAE18
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SPDIF_OUT
| rowspan="7" |J1.138
| rowspan="7" |SAI2_MCLK
| rowspan="7" |CPU.SAI2_MCLK| rowspan="7" |TBDAJ15
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="6" |J1.140
| rowspan="6" |SAI2_RXC
| rowspan="6" |CPU.SAI2_RXC| rowspan="6" |TBDAJ16
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="7" |J1.142
| rowspan="7" |SAI2_RXD0
| rowspan="7" |CPU.SAI2_RXD0| rowspan="7" |TBDAJ14
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |J1.144
| rowspan="7" |SAI2_RXFS
| rowspan="7" |CPU.SAI2_RXFS| rowspan="7" |TBDAH17
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="5" |J1.146
| rowspan="5" |SAI2_TXC
| rowspan="5" |CPU.SAI2_TXC| rowspan="5" |TBDAH15
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="6" |J1.148
| rowspan="6" |SAI2_TXD0
| rowspan="6" |CPU.SAI2_TXD0| rowspan="6" |TBDAH16
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="7" |J1.150
| rowspan="7" |SAI2_TXFS
| rowspan="7" |CPU.SAI2_TXFS| rowspan="7" |TBDAJ17
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="6" |SAI3_MCLK//
ISP_PRELIGHT_TRIG_0
| rowspan="6" |CPU.SAI3_MCLK| rowspan="6" |TBDAJ20
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_MCLK
| rowspan="7" |SAI3_RXC//
ISP_SHUTTER_OPEN_0
| rowspan="7" |CPU.SAI3_RXC| rowspan="7" |TBDAJ18
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_BCLK
| rowspan="6" |SAI3_RXD//
ISP_FL_TRIG_1
| rowspan="6" |CPU.SAI3_RXD| rowspan="6" |TBDAF18
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_DATA[0]
| rowspan="7" |SAI3_RXFS//
ISP_SHUTTER_TRIG_1
| rowspan="7" |CPU.SAI3_RXFS| rowspan="7" |TBDAJ19
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_RX_SYNC
| rowspan="7" |SAI3_TXC//
ISP_FLASH_TRIG_1
| rowspan="7" |CPU.SAI3_TXC| rowspan="7" |TBDAH19
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_BCLK
| rowspan="7" |SAI3_TXD//
ISP_PRELIGHT_TRIG_1
| rowspan="7" |CPU.SAI3_TXD| rowspan="7" |TBDAH18
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_DATA[0]
| rowspan="7" |SAI3_TXFS//
ISP_SHUTTER_OPEN_1
| rowspan="7" |CPU.SAI3_TXFS| rowspan="7" |TBDAC16
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSPDIF or ISP (*)
|Pin ALT-0
|AUDIOMIX_SAI3_TX_SYNC
| rowspan="6" |J1.166
| rowspan="6" |SAI5_MCLK
| rowspan="6" |CPU.SAI5_MCLK| rowspan="6" |TBDAF14
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |J1.168
| rowspan="6" |SAI5_RXC
| rowspan="6" |CPU.SAI5_RXC| rowspan="6" |TBDAD14
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |SAI5_RXD0//
ISO_14443_LA
| rowspan="6" |CPU.SAI5_RXD0| rowspan="6" |TBDAE16
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |Hardware mounting option depending on order codeSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[0]
| rowspan="7" |SAI5_RXD1//
ISO_14443_LB
| rowspan="7" |CPU.SAI5_RXD1| rowspan="7" |TBDAD16
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[1]
| rowspan="7" |SAI5_RXD2//
ISO_7816_CLK
| rowspan="7" |CPU.SAI5_RXD2| rowspan="7" |TBDAF16
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[2]
| rowspan="7" |SAI5_RXD3//
ISO_7816_RST_N
| rowspan="7" |CPU.SAI5_RXD3| rowspan="7" |TBDAE14
| rowspan="7" |NVCC_3V3
| rowspan="7" |I/O
| rowspan="7" |Hardware mounting option depending on order codeSAI5 or SE050 ISO (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_DATA[3]
| rowspan="5" |SAI5_RXFS//
SE050_ENA
| rowspan="5" |CPU.SAI5_RXFS| rowspan="5" |TBDAC14
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |Hardware mounting option depending on order codeSAI5 or SE050 (**)
|Pin ALT-0
|AUDIOMIX_SAI5_RX_SYNC
| rowspan="4" |J1.182
| rowspan="4" |SAI1_MCLK
| rowspan="4" |CPU.SAI1_MCLK| rowspan="4" |TBDAE12
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.184
| rowspan="4" |SAI1_RXC
| rowspan="4" |CPU.SAI1_RXC| rowspan="4" |TBDAH8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="5" |J1.186
| rowspan="5" |SAI1_RXD0
| rowspan="5" |CPU.SAI1_RXD0| rowspan="5" |TBDAC10
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="4" |J1.188
| rowspan="4" |SAI1_RXD1
| rowspan="4" |CPU.SAI1_RXD1| rowspan="4" |TBDAF10
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="5" |J1.190
| rowspan="5" |SAI1_RXD2
| rowspan="5" |CPU.SAI1_RXD2| rowspan="5" |TBDAH9
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.192
| rowspan="5" |SAI1_RXD3
| rowspan="5" |CPU.SAI1_RXD3| rowspan="5" |TBDAJ8
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.194
| rowspan="5" |SAI1_RXD4
| rowspan="5" |CPU.SAI1_RXD4| rowspan="5" |TBDAD10
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="6" |J1.196
| rowspan="6" |SAI1_RXD5
| rowspan="6" |CPU.SAI1_RXD5| rowspan="6" |TBDAE10
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="5" |J1.198
| rowspan="5" |SAI1_RXD6
| rowspan="5" |CPU.SAI1_RXD6| rowspan="5" |TBDAH10
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="6" |J1.200
| rowspan="6" |SAI1_RXD7
| rowspan="6" |CPU.SAI1_RXD7| rowspan="6" |TBDAH12
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="3" |J1.202
| rowspan="3" |SAI1_RXFS
| rowspan="3" |CPU.SAI1_RXFS| rowspan="3" |TBDAJ9
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="4" |J1.204
| rowspan="4" |SAI1_TXC
| rowspan="4" |CPU.SAI1_TXC| rowspan="4" |TBDAJ12
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.206
| rowspan="4" |SAI1_TXD0
| rowspan="4" |CPU.SAI1_TXD0| rowspan="4" |TBDAJ11
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.208
| rowspan="4" |SAI1_TXD1
| rowspan="4" |CPU.SAI1_TXD1| rowspan="4" |TBDAJ10
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.210
| rowspan="4" |SAI1_TXD2
| rowspan="4" |CPU.SAI1_TXD2| rowspan="4" |TBDAH11
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |J1.212
| rowspan="4" |SAI1_TXD3
| rowspan="4" |CPU.SAI1_TXD3| rowspan="4" |TBDAD12
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="5" |J1.214
| rowspan="5" |SAI1_TXD4
| rowspan="5" |CPU.SAI1_TXD4| rowspan="5" |TBDAH13
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.216
| rowspan="5" |SAI1_TXD5
| rowspan="5" |CPU.SAI1_TXD5| rowspan="5" |TBDAH14
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.218
| rowspan="5" |SAI1_TXD6
| rowspan="5" |CPU.SAI1_TXD6| rowspan="5" |TBDAC12
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |J1.220
| rowspan="5" |SAI1_TXD7
| rowspan="5" |CPU.SAI1_TXD7| rowspan="5" |TBDAJ13
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="4" |J1.222
| rowspan="4" |SAI1_TXFS
| rowspan="4" |CPU.SAI1_TXFS| rowspan="4" |TBDAF12
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|J1.226
(TPM SE on board)
|I2C1_SCL//
I2C_SCL_SE050
|TPMSE.ISO 7816 IO2
|16
|TPM_VOUTSE_VOUT
|I/O
|see SE section for
 
more details
|
|TBD
|
|-
I2C_SCL_SE050
| rowspan="4" |CPU.I2C1_SCL
| rowspan="4" |TBDAC8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
|-
|J1.228
(TPM SE on board)
|I2C1_SDA//
I2C_SDA_SE050
|TPMSE.ISO 7816 IO1
|3
|TPM_VOUTSE_VOUT
|I/O
|see SE section for
 
more details
|
|TBD
|
|-
I2C_SDA_SE050
| rowspan="4" |CPU.I2C1_SDA
| rowspan="4" |TBDAH7
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="6" |I2C2_SCL
| rowspan="6" |CPU.I2C2_SCL
| rowspan="6" |TBDAH6
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="5" |I2C2_SDA
| rowspan="5" |CPU.I2C2_SDA
| rowspan="5" |TBDAE8
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |I2C3_SCL
| rowspan="5" |CPU.I2C3_SCL
| rowspan="5" |TBDAJ7
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |I2C3_SDA
| rowspan="5" |CPU.I2C3_SDA
| rowspan="5" |TBDAJ6
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="5" |I2C4_SCL
| rowspan="5" |CPU.I2C4_SCL
| rowspan="5" |TBDAF8
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
| rowspan="4" |I2C4_SDA
| rowspan="4" |CPU.I2C4_SDA
| rowspan="4" |TBDAD8
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="3" |UART1_RXD
| rowspan="3" |CPU.UART1_RXD
| rowspan="3" |TBDAD6
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="3" |UART1_TXD
| rowspan="3" |CPU.UART1_TXD
| rowspan="3" |TBDAJ13
| rowspan="3" |NVCC_3V3
| rowspan="3" |I/O
| rowspan="4" |UART2_RXD
| rowspan="4" |CPU.UART2_RXD
| rowspan="4" |TBDAF6
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="4" |UART2_TXD
| rowspan="4" |CPU.UART2_TXD
| rowspan="4" |TBDAH4
| rowspan="4" |NVCC_3V3
| rowspan="4" |I/O
| rowspan="6" |UART3_RXD
| rowspan="6" |CPU.UART3_RXD
| rowspan="6" |TBDAE6
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |UART3_TXD
| rowspan="6" |CPU.UART3_TXD
| rowspan="6" |TBDAJ4
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="6" |UART4_RXD
| rowspan="6" |CPU.UART4_RXD
| rowspan="6" |TBDAJ15
| rowspan="6" |NVCC_3V3
| rowspan="6" |I/O
| rowspan="5" |UART4_TXD
| rowspan="5" |CPU.UART4_TXD
| rowspan="5" |TBDAH5
| rowspan="5" |NVCC_3V3
| rowspan="5" |I/O
|-
|}
'''(*)''' SPIDF and ISP signals cannot be present at the same time. ISP signals are in alternative to NAND and eMMC usage (see i.MX8Plus NAND controller on Reference Manual for more details). Please contact [mailto:sales@dave.eu sales] for more information
'''(**)''' SAI5 and SE050 ISO interface cannot be present at the same time. Please contact [mailto:sales@dave.eu sales] for more information
----
[[Category:ORCA]]
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