ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/JTAG
| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 1.0.0 | Dec 2021 | First release | |
JTAG interface[edit | edit source]
JTAG interface allow the developer to access every peripheral of the SoC using a debugger.
It is also possible to add the ETH1 PHY to the JTAG daisy chain (with a custom BOM).
The TRACE interface can be made available in alternative to the NAND or eMMC memory flash on board of the SoM.
Description[edit | edit source]
The JTAG interface available on the Evaluation Kit at the connector JD1.
JD1 is a 10x1x2.54mm strip header connector and it is not mounted.
Signals[edit | edit source]
The following table describes the interface signals:
| Pin# | Pin name | Function | ARM-20 JTAG | Notes |
|---|---|---|---|---|
| 1 | DGND | - | 4,6,8,10,12,14,16,18,20 | For example documented on Lauterbach specification |
| 2 | JTAG_TCK | - | 9 | - |
| 3 | JTAG_TMS | - | 7 | - |
| 4 | JTAG_TDO | - | 13 | - |
| 5 | JTAG_TDI | - | 5 | - |
| 6 | JTAG_MOD | - | - | 10K pull-down inside the SoM |
| 7 | CPU_PORn | - | 15 (*) | - |
| 8 | N.C. | - | - | - |
| 9 | N.C. | - | - | - |
| 10 | JTAG_VREF | - | 1 | 3V3 (BOARD_PGOOD driven signal) |
(*) optional signals, keep the possibility to be unconnected.
