Difference between revisions of "ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/JTAG"

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==JTAG interface ==
 
==JTAG interface ==
  
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica e del suo connettore''
+
JTAG interface allow the developer to access every peripheral of the SoC using a debugger.
−
''Nell'esempio di seguito c'è la descrizione dell'interfaccia UART/console''
+
 
 +
It is also possible to add the ETH1 PHY to the JTAG daisy chain (with a custom BOM).
 +
 
 +
The TRACE interface can be made available in alternative to the NAND or eMMC memory flash on board of the SoM.
  
 
=== Description  ===
 
=== Description  ===
  
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The JTAG interface available on the Evaluation Kit at the connector ''TBD:Jxxx''.
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The JTAG interface available on the Evaluation Kit at the connector ''JD1.''  
  
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''Jxx'' is a ''TBD:connector-type'' header connector for the RS232 two-wires UART3 port, used for debug purposes (bootloader and operating system serial console).
+
''JD1'' is a 10x1x2.54mm strip header connector and it is not mounted.
  
  
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{| class="wikitable"  
 
{| class="wikitable"  
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! latexfontsize="scriptsize"| Pin#
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! latexfontsize="scriptsize" | Pin#
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! latexfontsize="scriptsize"| SOM Pin#
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! latexfontsize="scriptsize" | Pin name
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! latexfontsize="scriptsize"| Pin name
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! latexfontsize="scriptsize" |Function
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! latexfontsize="scriptsize"| Pin function
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! latexfontsize="scriptsize" |'''ARM-20 JTAG'''
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! latexfontsize="scriptsize"| Pin Notes
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! latexfontsize="scriptsize" | Notes
 +
|-
 +
|1
 +
|DGND
 +
| -
 +
|4,6,8,10,12,14,16,18,20
 +
|For example documented on [https://www2.lauterbach.com/pdf/app_arm_jtag.pdf#page=3 Lauterbach specification]
 +
|-
 +
|2
 +
|JTAG_TCK
 +
| -
 +
|9
 +
| -
 +
|-
 +
|3
 +
|JTAG_TMS
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| -
 +
|7
 +
| -
 +
|-
 +
|4
 +
|JTAG_TDO
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| -
 +
|13
 +
| -
 +
|-
 +
|5
 +
|JTAG_TDI
 +
| -
 +
|5
 +
| -
 
|-
 
|-
−
|1,2,4,6,,7,8,10
+
|6
 +
|JTAG_MOD
 
| -
 
| -
−
| N.A.
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|'''''TBD''''' (*)
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| N.C.
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|10K pull-down inside the SoM
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| Not connected
 
 
|-
 
|-
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| 3
+
|7
−
| J1.189
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|CPU_PORn
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| RS232_RX
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| -
−
| Receive line
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|15 (*)
−
|  
+
| -
 
|-
 
|-
−
| 3
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|8
−
| J1.187
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|N.C.
−
| RS232_TX
+
| -
−
| Transmit line
+
|
−
|  
+
| -
 
|-
 
|-
−
| 9
+
|9
 +
|N.C.
 
| -
 
| -
−
| DGND
+
|
−
| Ground
+
| -
−
|  
+
|-
 +
|10
 +
|JTAG_VREF
 +
| -
 +
|1
 +
|3V3 (BOARD_PGOOD driven signal)
 
|}
 
|}
−
 
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(*) optional signals, keep the possibility to be unconnected.
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=== Device mapping ===
 
−
UART3 is mapped to <code>/dev/ttymxc2</code> device in Linux. The peripheral is used as the default serial console, both for the bootloader and the kernel.
 
−
 
 
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=== Device usage ===
 
−
 
 
−
To connect to the debug serial port:
 
−
 
 
−
# connect the DB9 adapter bracket to the J22 connector on the SBCX board
 
−
# connect a serial cable between DB9 connector and PC COM port through a NULL-modem cable (not provided)
 
−
# start your favorite terminal emulator software on PC (eg: PuTTY); communication parameters are: 115200,N,8,1
 
−
 
 
 
----
 
----
  
 
[[Category:ORCA SOM]]
 
[[Category:ORCA SOM]]

Revision as of 13:27, 6 September 2021

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History
Version Issue Date Notes
1.0.0 Sep 2021 First release


JTAG interface[edit | edit source]

JTAG interface allow the developer to access every peripheral of the SoC using a debugger.

It is also possible to add the ETH1 PHY to the JTAG daisy chain (with a custom BOM).

The TRACE interface can be made available in alternative to the NAND or eMMC memory flash on board of the SoM.

Description[edit | edit source]

The JTAG interface available on the Evaluation Kit at the connector JD1.

JD1 is a 10x1x2.54mm strip header connector and it is not mounted.


[[File:{Template:Nome-som-EVB-JTAG-connector.png|thumb|center|500px|JTAG connector]]

Signals[edit | edit source]

The following table describes the interface signals:

Pin# Pin name Function ARM-20 JTAG Notes
1 DGND - 4,6,8,10,12,14,16,18,20 For example documented on Lauterbach specification
2 JTAG_TCK - 9 -
3 JTAG_TMS - 7 -
4 JTAG_TDO - 13 -
5 JTAG_TDI - 5 -
6 JTAG_MOD - TBD (*) 10K pull-down inside the SoM
7 CPU_PORn - 15 (*) -
8 N.C. - -
9 N.C. - -
10 JTAG_VREF - 1 3V3 (BOARD_PGOOD driven signal)

(*) optional signals, keep the possibility to be unconnected.

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